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? motorola, inc., 1998 hc05sb7grs/h rev 2.1 68HC05SB7 68hc705sb7 specification (general release) august 27, 1998 consumer systems group semiconductor products sector motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.

august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 i table of contents section page section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask option ................................................................................................ 1-2 1.3 peprom factory preprogrammed options ................................... 1-2 1.4 mcu structure.......................................................................................... 1-2 1.5 pin assignments ........................................................................................ 1-4 1.6 functional pin description.................................................................. 1-4 1.6.1 vdd, vss .................................................................................................... 1-4 1.6.2 osc1, osc2 ............................................................................................... 1-4 1.6.3 irq /vpp ...................................................................................................... 1-5 1.6.4 reset ......................................................................................................... 1-6 1.6.5 csa ............................................................................................................. 1-6 1.6.6 tm................................................................................................................ 1-6 1.6.7 vm ............................................................................................................... 1-6 1.6.8 cap (adc) .................................................................................................. 1-6 1.6.9 esv.............................................................................................................. 1-7 1.6.10 pa0-pa7 / pwm0-pwm3, scl0-scl1, sda0-sda1 ................................. 1-7 1.6.11 pb1-pb7 / tcap, cs0-cs1, an0-an3 ....................................................... 1-7 1.6.12 pc4-pc7...................................................................................................... 1-7 section 2 memory 2.1 memory map ................................................................................................ 2-1 2.2 input/output section.............................................................................. 2-2 2.3 interrupt vector mapping ................................................................... 2-6 2.4 rom................................................................................................................. 2-6 2.5 ram ................................................................................................................. 2-6 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.2 accumulator (a)........................................................................................ 3-2 3.3 index register (x) ..................................................................................... 3-2 3.4 stack pointer (sp) .................................................................................... 3-2 3.5 program counter (pc) ........................................................................... 3-2 3.6 condition code register (ccr) ........................................................... 3-3 3.6.1 half carry bit (h-bit) .................................................................................... 3-3 3.6.2 interrupt mask (i-bit) .................................................................................... 3-3 3.6.3 negative bit (n-bit) ...................................................................................... 3-3 3.6.4 zero bit (z-bit) ............................................................................................. 3-3 3.6.5 carry/borrow bit (c-bit) ............................................................................... 3-4
general release specification august 27, 1998 motorola mc68HC05SB7 ii rev 2.1 table of contents section page section 4 interrupts 4.1 interrupt vectors .................................................................................. 4-1 4.2 interrupt processing............................................................................ 4-2 4.3 software interrupt ............................................................................... 4-4 4.4 external interrupt................................................................................. 4-4 4.4.1 irq /vpp pin ................................................................................................ 4-4 4.4.2 irq status and control register (iscr) ..................................................... 4-5 4.5 core timer interrupts........................................................................... 4-6 4.5.1 core timer overflow interrupt ..................................................................... 4-7 4.5.2 real-time interrupt...................................................................................... 4-7 4.6 programmable timer interrupts ...................................................... 4-7 4.6.1 input capture interrupt................................................................................. 4-7 4.6.2 output compare interrupt............................................................................ 4-7 4.6.3 timer overflow interrupt .............................................................................. 4-7 4.7 sm-bus interrupt...................................................................................... 4-8 4.8 analog interrupts .................................................................................. 4-8 4.8.1 comparator input match interrupt................................................................ 4-8 4.8.2 input capture interrupt................................................................................. 4-8 4.9 current detect interrupt................................................................... 4-8 section 5 resets 5.1 power-on reset ........................................................................................ 5-2 5.2 external reset ......................................................................................... 5-2 5.3 internal resets ........................................................................................ 5-2 5.3.1 power-on reset (por) ............................................................................... 5-2 5.3.2 computer operating properly (cop) reset ................................................ 5-3 5.3.3 low voltage reset (lvr) ............................................................................ 5-4 5.3.4 illegal address reset................................................................................... 5-4 5.4 reset states .............................................................................................. 5-4 5.4.1 cpu ............................................................................................................. 5-4 5.4.2 i/o registers................................................................................................ 5-4 5.4.3 core timer................................................................................................... 5-5 5.4.4 cop watchdog............................................................................................ 5-5 5.4.5 16-bit programmable timer......................................................................... 5-5 5.4.6 sm-bus serial interface............................................................................... 5-5 5.4.7 analog subsystem....................................................................................... 5-6 section 6 low power modes 6.1 stop mode.................................................................................................... 6-3 6.2 wait mode .................................................................................................... 6-4
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 iii table of contents section page 6.3 data-retention mode.............................................................................. 6-4 6.4 slow mode................................................................................................... 6-5 section 7 input/output ports 7.1 parallel ports.......................................................................................... 7-1 7.1.1 port data registers ..................................................................................... 7-2 7.1.2 port data direction registers ...................................................................... 7-2 7.2 port a............................................................................................................ 7-2 7.3 port b............................................................................................................ 7-2 7.4 port c............................................................................................................ 7-2 section 8 system clock 8.1 clock sources .......................................................................................... 8-1 8.2 vco clock speed....................................................................................... 8-2 8.2.1 vco slow mode .......................................................................................... 8-2 8.2.2 setting the vco speed ............................................................................... 8-3 section 9 core timer 9.1 core timer status and control register..................................... 9-2 9.2 core timer counter register (ctcr) ............................................... 9-3 9.3 cop watchdog ........................................................................................... 9-4 9.4 core timer during wait mode.............................................................. 9-5 9.5 core timer during stop mode............................................................. 9-5 section 10 16-bit timer 10.1 timer registers (tmrh, tmrl)............................................................. 10-2 10.2 alternate counter registers (acrh, acrl) ................................ 10-4 10.3 input capture registers .................................................................... 10-5 10.4 output compare registers ............................................................... 10-7 10.5 timer control register (tcr) ........................................................... 10-9 10.6 timer status register (tsr)............................................................. 10-10 10.7 timer operation during wait mode............................................... 10-11 10.8 timer operation during stop mode .............................................. 10-11 section 11 pulse width modulator 11.1 d/a data registers (dac0-dac3) ......................................................... 11-2 11.2 mux channel enable register (mcer) ............................................ 11-3 11.3 pwm during wait mode ......................................................................... 11-4 11.4 pwm during stop mode......................................................................... 11-4
general release specification august 27, 1998 motorola mc68HC05SB7 iv rev 2.1 table of contents section page section 12 sm-bus 12.1 sm-bus introduction............................................................................. 12-1 12.2 sm-bus interface features................................................................ 12-1 12.3 sm-bus system configuration .......................................................... 12-2 12.4 sm-bus protocol .................................................................................... 12-2 12.4.1 start signal ............................................................................................ 12-3 12.4.2 slave address transmission ..................................................................... 12-3 12.4.3 data transfer............................................................................................. 12-3 12.4.4 repeated start signal ........................................................................... 12-4 12.4.5 stop signal .............................................................................................. 12-4 12.4.6 arbitration procedure................................................................................. 12-4 12.4.7 clock synchronization ............................................................................... 12-5 12.4.8 handshaking.............................................................................................. 12-5 12.5 sm-bus registers ................................................................................... 12-5 12.5.1 sm-bus address register (smadr) ......................................................... 12-6 12.5.2 sm-bus frequency divider register (smfdr) ......................................... 12-6 12.5.3 sm-bus control register (smcr) ............................................................. 12-7 12.5.4 sm-bus status register (smsr)............................................................... 12-8 12.5.5 sm-bus data i/o register (smdr) ......................................................... 12-10 12.5.6 sm-bus logic level .................................................................................. 12-10 12.5.7 scl as16-bit timer input capture ........................................................... 12-10 12.6 programming considerations........................................................ 12-11 12.6.1 initialization .............................................................................................. 12-11 12.6.2 generation of a start signal and the first byte of data transfer ........ 12-11 12.6.3 software responses after transmission or reception of a byte ............ 12-11 12.6.4 generation of the stop signal ............................................................... 12-13 12.6.5 generation of a repeated start signal................................................ 12-14 12.6.6 slave mode.............................................................................................. 12-14 12.6.7 arbitration lost......................................................................................... 12-14 12.7 operation during wait mode ........................................................... 12-14 12.8 operation during stop mode .......................................................... 12-14 section 13 current sense amplifier 13.1 current sense amplifier application............................................ 13-1 13.2 current sense interrupt................................................................... 13-2 13.3 csa status and control register (csscr) .................................. 13-2 13.4 csa operation during wait mode..................................................... 13-4 13.5 csa operation during stop mode.................................................... 13-4
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 v table of contents section page section 14 temperature sensor 14.1 internal temperature sensor ......................................................... 14-1 14.2 external temperature sensor........................................................ 14-2 14.3 temperature sensor operation during wait mode................. 14-2 14.4 temperature sensor operation during stop mode................ 14-2 section 15 analog subsystem 15.1 analog multiplex registers ............................................................. 15-3 15.2 analog control register ................................................................ 15-14 15.3 analog status register.................................................................... 15-17 15.4 a/d conversion methods ................................................................... 15-19 15.5 voltage measurement methods .................................................... 15-27 15.5.1 absolute voltage readings ..................................................................... 15-27 15.5.2 ratiometric voltage readings ................................................................. 15-28 15.6 voltage comparator features ..................................................... 15-29 15.7 current source features ............................................................... 15-30 15.8 sample and hold ................................................................................... 15-30 15.9 port b interaction with analog inputs ...................................... 15-30 15.9.1 port b pins as inputs............................................................................... 15-31 15.10 noise sensitivity ............................................................................................................ 15 -31 section 16 personality eprom 16.1 peprom registers.................................................................................. 16-2 16.1.1 peprom bit select register (pebsr) ..................................................... 16-2 16.1.2 peprom status and control register (pescr) ...................................... 16-2 16.2 peprom programming........................................................................... 16-3 16.3 peprom reading ...................................................................................... 16-4 16.4 peprom erasing ...................................................................................... 16-4 16.5 peprom preprogrammed options ................................................... 16-5 16.5.1 data format in preprogrammed peprom ............................................... 16-5 section 17 instruction set 17.1 addressing modes ................................................................................. 17-1 17.1.1 inherent...................................................................................................... 17-1 17.1.2 immediate .................................................................................................. 17-1 17.1.3 direct ......................................................................................................... 17-2 17.1.4 extended.................................................................................................... 17-2 17.1.5 indexed, no offset..................................................................................... 17-2 17.1.6 indexed, 8-bit offset .................................................................................. 17-2
general release specification august 27, 1998 motorola mc68HC05SB7 vi rev 2.1 table of contents section page 17.1.7 indexed, 16-bit offset ................................................................................ 17-3 17.1.8 relative...................................................................................................... 17-3 17.1.9 instruction types ....................................................................................... 17-3 17.1.10 register/memory instructions .................................................................... 17-4 17.1.11 read-modify-write instructions ................................................................. 17-5 17.1.12 jump/branch instructions .......................................................................... 17-5 17.1.13 bit manipulation instructions...................................................................... 17-7 17.1.14 control instructions.................................................................................... 17-7 17.1.15 instruction set summary ........................................................................... 17-8 section 18 electrical specifications 18.1 maximum ratings..................................................................................... 18-1 18.2 operating temperature range ........................................................ 18-1 18.3 thermal characteristics ................................................................... 18-1 18.4 supply current characteristics ................................................... 18-2 18.5 peprom programming characteristics........................................ 18-2 18.6 dc electrical characteristics........................................................ 18-3 18.7 analog subsystem characteristics .............................................. 18-4 18.8 control timing ........................................................................................ 18-5 18.9 reset characteristics ........................................................................ 18-6 18.10 sm-bus dc electrical characteristics......................................... 18-8 18.11 sm-bus control timing ......................................................................... 18-8 18.11.1 sm-bus interface input signal timing ....................................................... 18-8 18.11.2 sm-bus interface output signal timing .................................................... 18-8 section 19 mechanical specifications 19.1 28-pin soic (case 751f)............................................................................ 19-1 19.2 28-pin ssop ................................................................................................. 19-2 appendix a mc68hc705sb7 a.1 introduction..............................................................................................a-1 a.2 memory .........................................................................................................a-1 a.3 personality eprom (peprom)...............................................................a-2 a.4 mask option register.............................................................................a-2 a.5 bootloader mode ....................................................................................a-3 a.6 eprom programming ...............................................................................a-3 a.6.1 eprom programming register (eprog) ..................................................a-3 a.6.2 programming sequence ..............................................................................a-4 a.7 eprom erasing...........................................................................................a-5 a.8 eprom programming specifications ................................................a-6
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 vii list of figures figure title page 1-1 mc68HC05SB7 block diagram ....................................................................... 1-3 1-2 mc68HC05SB7 pin assignments.................................................................... 1-4 1-3 epo oscillator connections............................................................................. 1-5 2-1 mc68HC05SB7 memory map.......................................................................... 2-1 2-2 mc68HC05SB7 i/o registers.......................................................................... 2-2 2-3 mc68HC05SB7 i/o registers $0000-$000f ................................................... 2-3 2-4 mc68HC05SB7 i/o registers $0010-$001f ................................................... 2-4 2-5 mc68HC05SB7 i/o registers $0020-$002f ................................................... 2-5 2-6 cop register (copr) ..................................................................................... 2-5 2-7 mc68HC05SB7 interrupt vector mapping ....................................................... 2-6 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt stacking order................................................................................... 4-2 4-2 interrupt flow chart ......................................................................................... 4-3 4-3 external interrupt logic .................................................................................... 4-5 4-4 irq status and control register (iscr).......................................................... 4-5 5-1 reset sources.................................................................................................. 5-1 5-2 cop watchdog register (copr) .................................................................... 5-3 5-3 miscellaneous control register (mcr)............................................................ 5-3 6-1 stop and wait flowchart.............................................................................. 6-2 6-2 miscellaneous control register (mcr)............................................................ 6-5 7-1 port i/o circuitry............................................................................................... 7-1 8-1 mc68HC05SB7 input clock source ................................................................ 8-1 8-2 irq status and control register (iscr).......................................................... 8-2 8-3 miscellaneous control register (mcr)............................................................ 8-3 8-4 vco adjust register (var) ............................................................................. 8-3 9-1 core timer block diagram............................................................................... 9-1 9-2 core timer status and control register (ctscr) .......................................... 9-2 9-3 core timer counter register (ctcr).............................................................. 9-3 9-4 cop watchdog register (copr) .................................................................... 9-4 9-5 miscellaneous control register (mcr)............................................................ 9-4 10-1 programmable timer block diagram ............................................................. 10-1 10-2 programmable timer block diagram ............................................................. 10-2 10-3 programmable timer registers (tmrh, tmrl)............................................ 10-3 10-4 alternate counter block diagram................................................................... 10-4 10-5 alternate counter registers (acrh, acrl).................................................. 10-4 10-6 timer input capture block diagram............................................................... 10-5 10-7 miscellaneous control register (mcr).......................................................... 10-5 10-8 analog control register (acr) ...................................................................... 10-6 10-9 input capture registers (icrh, icrl)........................................................... 10-6 10-10 timer output compare block diagram .......................................................... 10-7 10-11 output compare registers (ocrh, ocrl) .................................................. 10-8 10-12 timer control register (tcr) ........................................................................ 10-9 10-13 timer status registers (tsr) ...................................................................... 10-10
general release specification august 27, 1998 motorola mc68HC05SB7 viii rev 2.1 list of figures figure title page 11-1 pwm block diagram ...................................................................................... 11-1 11-2 d/a data register 0 (dac0) (msb) ............................................................... 11-2 11-3 d/a data register 0 (dac0) (lsb) ................................................................ 11-2 11-4 d/a data register 1 (dac1) (msb) ............................................................... 11-2 11-5 d/a data register 1 (dac1) (lsb) ................................................................ 11-2 11-6 d/a data register 2 (dac2) (msb) ............................................................... 11-2 11-7 d/a data register 2 (dac2) (lsb) ................................................................ 11-2 11-10 pwm output waveform examples ................................................................ 11-3 11-8 d/a data register 3 (dac3) (msb) ............................................................... 11-3 11-9 d/a data register 3 (dac3) (lsb) ................................................................ 11-3 11-11 mux channel enable register (mcer) ........................................................ 11-4 12-1 sm-bus interface block diagram ................................................................... 12-2 12-2 sm-bus transmission signal diagram .......................................................... 12-3 12-3 clock synchronization.................................................................................... 12-5 12-4 miscellaneous control register (mcr)........................................................ 12-10 12-5 flow-chart of sm-bus interrupt routine....................................................... 12-12 13-1 current sense amplifier block ....................................................................... 13-2 13-2 csa status and control register (csscr)................................................... 13-3 13-3 miscellaneous control register (mcr).......................................................... 13-4 14-1 miscellaneous control register (mcr).......................................................... 14-1 14-2 external temperature sensor connection..................................................... 14-2 15-1 analog subsystem block diagram................................................................. 15-2 15-2 analog multiplex register 1 (amux1)............................................................ 15-3 15-3 analog multiplex register 2 (amux2)............................................................ 15-3 15-4 inv bit action ................................................................................................. 15-4 15-5 analog control register (acr) .................................................................... 15-14 15-6 analog status register ................................................................................ 15-17 15-7 single-slope a/d conversion method.......................................................... 15-19 15-8 a/d conversion - full manual control (mode 0) .......................................... 15-23 15-9 a/d conversion - manual/auto discharge control (mode 1) ....................... 15-24 15-10 a/d conversion - tof/icf control (mode 2)............................................... 15-25 15-11 a/d conversion - ocf/icf control (mode 3) .............................................. 15-26 16-1 personality eprom ....................................................................................... 16-1 16-2 peprom bit select register (pebsr) ......................................................... 16-2 16-3 peprom status and control register (pescr)........................................... 16-2 18-1 stop recovery timing diagram ..................................................................... 18-6 18-2 internal reset timing diagram ...................................................................... 18-7 18-3 low voltage reset timing diagram............................................................... 18-7 18-4 sm-bus timing diagram ................................................................................ 18-9 a-1 mc68hc705sb7 memory map........................................................................a-1 a-2 mc68hc705sb7 mask option register (mor ...............................................a-2 a-3 eprom programming register (eprog).......................................................a-3 a-4 eprom programming sequence ....................................................................a-5
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 ix list of tables table title page 4-1 reset/interrupt vector addresses .................................................................... 4-1 7-1 i/o pin functions.............................................................................................. 7-1 8-1 clock source selection .................................................................................... 8-2 9-1 core timer interrupt rates and cop timeout selection................................. 9-3 10-1 16-bit timer input capture source................................................................. 10-6 12-1 sm-bus clock prescaler ................................................................................ 12-6 13-1 voltage across the sense resistor against current ...................................... 13-1 13-2 current sense amplifier gain select ............................................................. 13-3 13-3 current detect output select ......................................................................... 13-4 15-1 comparator input sources ............................................................................. 15-3 15-2 channel select bus combinations................................................................. 15-6 15-3 a/d conversion options............................................................................... 15-15 15-4 a/d conversion signals and definitions ...................................................... 15-21 15-5 sample conversion timing .......................................................................... 15-22 15-6 absolute voltage reading errors................................................................. 15-27 15-7 ratiometric voltage reading errors............................................................. 15-29 15-8 voltage comparator setup conditions......................................................... 15-30 16-1 peprom bit selection................................................................................... 16-3 16-2 peprom preprogrammed option ................................................................. 16-5 17-1 register/memory instructions ........................................................................ 17-4 17-2 read-modify-write instructions ..................................................................... 17-5 17-3 jump and branch instructions........................................................................ 17-6 17-4 bit manipulation instructions .......................................................................... 17-7 17-5 control instructions ........................................................................................ 17-7 17-6 instruction set summary .............................................................................. 17-8 17-7 opcode map................................................................................................. 17-14
general release specification august 27, 1998 motorola mc68HC05SB7 x rev 2.1 list of tables table title page
august 27, 1998 general release specification mc68HC05SB7 general description motorola rev 2.1 1-1 section 1 general description the mc68HC05SB7 hcmos microcontroller is a member of the m68hc05 family of low-cost single-chip microcontrollers. this 8-bit microcontroller unit (mcu), which contains an internal oscillator, cpu, ram, rom, personality eprom, i/o, 16-bit timer, core timer, watchdog system, lvr, sm-bus, pwm, current sense ampli?r, internal temperature sensor and a/d, is designed speci?ally for smart battery applications. 1.1 features industry standard 8-bit m68hc05 cpu core power saving stop, wait, data-retention and slow modes 2.1mhz maximum bus frequency from internal vco or external pin oscillator 6144 bytes of user rom with the security feature 224 bytes of user ram (64 bytes for stack) system calibration characteristics by 64-bit personality eprom 19 bidirectional i/o lines 4 shared with sm-bus 4 shared with pwm 4 shared with a/d analog channels input 2 shared with current detect output 1 shared with timer input capture (tcap) 16-bit programmable timer with input capture/output compare (driven by interrupt) 15-stage multi-function core timer including 8-bit free-running counter and 4-stage selectable real-time interrupt generator built-in current sensing ampli?rs with selectable gain of 10 and 30 two voltage comparators which can be combined with the 16-bit timer to create an 8-channel, single-slope analog to digital converter built-in internal temperature sensor from 0 c to 70 c
general release specification august 27, 1998 motorola general description mc68HC05SB7 1-2 rev 2.1 4 channels 10-bit pwm running at a ?ed clock rate sm-bus ? serial interface compatible with i 2 c ?? bus slow ramp up power supply reset capability via lvr selectable sensitivity on irq interrupt (edge- and level-sensitive or edge-only) sm-bus, current detect, 16-bit timer, analog subsystem and core timer interrupts internal 100k w pull-up resistor on reset low voltage reset (lvr) illegal address reset computer operating properly (cop) watchdog system available in 28-pin ssop note a bar over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, or frequency speci?d in the following sections will refer to the nominal values. the exact values and their tolerance or limits are speci?d in the electrical speci?ations section. 1.2 mask option a single mask option is available on the mc68HC05SB7. external oscillator on pins osc1 and osc2 (epo): [enabled or disabled] 1.3 peprom factory preprogrammed options the mc68HC05SB7 is available with a factory preprogrammed peprom contain- ing any of the following measured parameters: the internal vco minimum frequency: programmed or left blank the internal vco maximum frequency: programmed or left blank the internal bandgap reference voltage: programmed or left blank the internal temperature sensor voltage at 80 c: programmed or left blank 1.4 mcu structure the block diagram of the mc68HC05SB7 is shown in figure 1-1 . ? sm-bus is an intel bus standard. ?? i 2 c bus is a philips bus standard.
august 27, 1998 general release specification mc68HC05SB7 general description motorola rev 2.1 1-3 figure 1-1. mc68HC05SB7 block diagram oscillator and divide by 2 stk ptr cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 alu 68hc05 cpu accum program counter cpu regis- port b reg data dir reg pb5/an2 pb2/cs0* pb3/cs1* pb4/an3 pb6/an1 pb7/an0 port c reg data dir reg pc5 pc4 pc6 pc7 port a reg data dir reg pa7/sda1 pa6/scl1 pa2/pwm2 pa5/sda0 pa4/scl0 pa3/pwm3 pa1/pwm1 pa0/pwm0 v ss v dd reset core timer low voltage irq /v pp illegal addr reset internal temperature sensor and bandgap reference current sense amplifier vm tm csa reset esv pb1/tcap v dd + comp tcap tcmp ocf tof icf 4 4 static ram - 224 bytes user rom - 6656 bytes personality eprom - 64 bits cap 4 tcap 2 an3:0 cs1:0 watchdog system v dd osc1* osc2* (pb2/cs0) (pb3/cs1) esven mux tcap scl tcsel * selected by mask option 16-bit timer 10-bit pwm sm-bus serial interface comparator control and multiplexer
general release specification august 27, 1998 motorola general description mc68HC05SB7 1-4 rev 2.1 1.5 pin assignments the mc68HC05SB7 is available in 28-pin ssop package. the pin assignments are shown in figure 1-2 . figure 1-2. mc68HC05SB7 pin assignments 1.6 functional pin description the following paragraphs give a description of the general function of each pin. 1.6.1 v dd , v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency char- acteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.6.2 osc1, osc2 when selected by a mask option, the osc1 and osc2 pins are the connections for the external pin oscillator (epo). the osc1 and osc2 pins can accept the fol- lowing sets of components: 1. a crystal as shown in figure 1-3 (a). 2. a ceramic resonator as shown in figure 1-3 (a). 3. an external clock signal as shown in figure 1-3 (b). 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 v ss csa v dd pb3/cs1 (osc2) cap(adc) pc4 pb2/cs0 (osc1) esv vm pc5 pc6 pc7 pa7/sda1 pa6/scl1 pa5/sda0 pa4/scl0 pa3/pwm3 12 13 14 pb6/an1 pb7/an0 17 16 15 pa2/pwm2 pa1/pwm1 pa0/pwm0 reset pb5/an2 pb4/an3 tm irq /vpp pb1/tcap
august 27, 1998 general release specification mc68HC05SB7 general description motorola rev 2.1 1-5 the frequency, f osc of the epo or external clock source is divided by two to pro- duce the internal operating frequency, f op . or f bus . crystal oscillator the circuit in figure 1-3 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturers recommendations should be fol- lowed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. figure 1-3. epo oscillator connections ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-3 (a) can be used for a ceramic resonator. the res- onator manufacturers recommendations should be followed, as the resonator parameters determine the external component values required for maximum sta- bility and reliable starting. the load capacitance values used in the oscillator cir- cuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for start-up stabi- lization and to minimize output distortion. external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-3 (b). this con?uration is possible regardless of whether the crystal/ceramic resonator or internal vco is enabled. 1.6.3 irq /v pp the irq /v pp input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a bit to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if the mcu osc1 osc2 2m w unconnected external clock mcu osc1 osc2 (a) crystal or ceramic resonator connections (b) external clock source connection
general release specification august 27, 1998 motorola general description mc68HC05SB7 1-6 rev 2.1 option is selected to include level-sensitive triggering, the irq /v pp input requires an external resistor to v dd for ?ired-or operation, if desired. if the irq /v pp pin is not used, it must be tied to the v dd supply. the irq /v pp pin contains an internal schmitt trigger as part of its input to improve noise immunity. the voltage on this pin may affect the mode of operation and should not exceed v dd . the irq /v pp pin is also used for programming voltage when programming the personality eprom. see section on interrupts for more details. 1.6.4 reset the reset pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. it also functions as an output to indicate that an internal cop watchdog, illegal address, or low voltage reset has occurred. the reset pin contains a pullup device to allow the pin to be left disconnected with- out an external pullup resistor. the reset pin also contains a steering diode that, when the power is removed, will discharge to v dd any charge left on an external capacitor connected between the reset pin and v ss . the reset pin also con- tains an internal schmitt trigger to improve its noise immunity as an input. see section on resets for more details. 1.6.5 csa this pin is the input to the current sense ampli?r. usually one terminal of the cur- rent path shunt sensing resistor of 0.01 w is connected to this input pin. the other terminal is connected to v ss . see section on current sense ampli?r for more details. 1.6.6 tm this pin is fed from the output of an external temperature sensor. usually a ther- mistor with a resistor forms a voltage divider with the voltage value applied to this input. see section on temperature sensor for more details. 1.6.7 vm this pin is the battery voltage input of the voltage measurement circuit. see section on temperature sensor for more details. 1.6.8 cap (adc) this pin is connected to an external ramp capacitor to form the slope voltage con- verter. see section on analog subsystem for more details.
august 27, 1998 general release specification mc68HC05SB7 general description motorola rev 2.1 1-7 1.6.9 esv this pin provides a switchable 5ma at v oh (at worst case) to an external eeprom. the esven bit in the miscellaneous control register enables/disables the esv pin. esven ?esv enable this read/write bit selects whether esv is enable or not. reset clears the esven bit. 1 = esv enabled. 0 = esv disabled. 1.6.10 pa0-pa7 / pwm0-pwm3, scl0-scl1, sda0-sda1 these eight i/o lines comprise the port a. the state of any pin is software pro- grammable and all port a lines are con?ured as inputs during power-on or reset. pa0-pa3 are multiplexed with pwm outputs pwm0-pwm3. pa4-pa7 are multi- plexed with the two sm-bus channels - scl0, sda0 and scl1, sda1. 1.6.11 pb1-pb7 / tcap, cs0-cs1, an0-an3 pins pb2/cs0 and pb3/cs1 are only available when selected by a mask option. these seven i/o lines comprise the port b. the state of any pin is software pro- grammable and all port b lines are con?ured as input during power-on or at reset. pb1 is con?ured as the tcap input pin for the 16-bit timer after a reset, and is disabled by setting the icen bit in the analog control register ($1d). pb2 and pb3 (when selected) are multiplexed with cs0 and cs1 respectively, from the current sense interrupt circuit. see section on current sense ampli?r for more details. pb4-pb7 are multiplexed with the analog input pins of the a/d converter. see sec- tion on analog subsystem for more details. 1.6.12 pc4-pc7 these four i/o lines comprise the port c. the state of any pin is software program- mable and all port c lines are con?ured as input during power-on or at reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset
general release specification august 27, 1998 motorola general description mc68HC05SB7 1-8 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 memory motorola rev 2.1 2-1 section 2 memory this section describes the organization of the mc68HC05SB7 on-chip memory. 2.1 memory map in normal operating mode, the 48 bytes of i/o, 224 bytes of user ram and 6144 bytes of user rom are all active as shown in figure 2-1 . the rom portion of memory holds the program instructions, ?ed data, user de?ed vectors, and interrupt service routines. the ram portion of memory holds variable data. i/o registers are memory mapped so that the cpu can access their locations in the same way that it accesses all other memory locations. $0000 i/o registers 48 bytes $002f $0030 unimplemented 16 bytes $003f $0040 user ram 224 bytes stack ram 64 bytes $00c0 $011f $00ff $0120 unimplemented 1248 bytes $05ff $0600 user rom 6144 bytes $1dff $1e00 internal test rom 496 bytes $1fef $1ff0 user vectors 16 bytes $1fff figure 2-1. mc68HC05SB7 memory map
general release specification august 27, 1998 motorola memory mc68HC05SB7 2-2 rev 2.1 2.2 input/output section the ?st 48 addresses of the memory space, $0000 ?$002f, are the i/o section as summarized in figure 2-2 . these are the addresses of the i/o control regis- ters, status registers, and data registers. reading from unimplemented locations will return unknown states, and writing to unimplemented locations will be ignored. one i/o register is located outside the 48-byte i/o section which is the computer operating properly (cop) register, mapped at $1ff0. the assignment of each control, status, and data bit in the i/o register space from $0000 through $002f are given in figure 2-3 , figure 2-4 , and figure 2-5 . addr. register name addr. register name $0000 port a data register $0018 timer counter register msb $0001 port b data register $0019 timer counter register lsb $0002 port c data register $001a alternate counter register msb $0003 analog mux register 1 $001b alternate counter register lsb $0004 port a data direction register $001c reserved $0005 port b data direction register $001d analog control register $0006 port c data direction register $001e analog status register $0007 analog mux register 2 $001f reserved $0008 core timer status & control register $0020 sm-bus address register $0009 core timer counter $0021 sm-bus frequency select register $000a csa status/control register $0022 sm-bus control register $000b miscellaneous control register $0023 sm-bus status register $000c vco adjust register $0024 sm-bus data register $000d irq status & control register $0025 d/a register 0 h $000e personality eprom bit select register $0026 d/a register 0 l $000f personality eprom status & control reg. $0027 d/a register 1 h $0010 reserved $0028 d/a register 1 l $0011 reserved $0029 d/a register 2 h $0012 timer control register $002a d/a register 2 l $0013 timer status register $002b d/a register 3 h $0014 input capture register msb $002c d/a register 3 l $0015 input capture register lsb $002d mux channel enable register $0016 output compare register msb $002e reserved $0017 output compare register lsb $002f reserved figure 2-2. mc68HC05SB7 i/o registers
august 27, 1998 general release specification mc68HC05SB7 memory motorola rev 2.1 2-3 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta w $0001 port b data r pb7 pb6 pb5 pb4 pb3 pb2 pb1 portb w $0002 port c data r pc7 pc6 pc5 pc4 portc w $0003 analog mux 1 r hold dhold inv vref mux3 mux2 mux1 mux0 amux1 w $0004 port a data direction r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra w $0005 port b data direction r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 0 ddrb w $0006 port c data direction r ddrc7 ddrc6 ddrc5 ddrc4 0000 ddrc w $0007 analog mux 2 r 0 0 iref mux7 mux6 mux5 mux4 amux2 w $0008 ctimer status/ctrl r ctof rtif ctofe rtie 00 rt1 rt0 ctscr w ctofr rtifr $0009 ctimer counter r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 ctcr w $000a csa status/control r csen x30 x10 cscal cden cdie 0 csif csascr w csifr $000b misc control r tsen lvron 0 sclk cssel tcsel esven sminlev mcr w copon $000c vco adjust r va4 va3 va2 va1 va0 var w $000d irq status/ctrl r irqe vcoen level 0 irqf 0 0 0 iscr w irqr $000e peprom bit select r peb7 peb7 peb7 peb4 peb3 peb2 peb1 peb0 pebsr w $000f peprom status/ctrl r pedata 0 pepgm 0 0 0 0 pepzrf pescr w unimplemented bits reserved bits figure 2-3. mc68HC05SB7 i/o registers $0000-$000f
general release specification august 27, 1998 motorola memory mc68HC05SB7 2-4 rev 2.1 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 reserved r w $0011 reserved r w $0012 timer control r icie ocie toie 000 iedg olvl tcr w $0013 timer status r icf ocf tof 00000 tsr w $0014 input capture msb r icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 icrh w $0015 input capture lsb r icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 icrl w $0016 output compare msb r ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 ocrh w $0017 output compare lsb r ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 ocrl w $0018 timer counter msb r tmrh7 tmrh6 tmrh5 tmrh4 tmrh3 tmrh2 tmrh1 tmrh0 tmrh w $0019 timer counter lsb r tmrl7 tmrl6 tmrl5 tmrl4 tmrl3 tmrl2 tmrl1 tmrl0 tmrl w $001a alter. counter msb r acrh7 acrh6 acrh5 acrh4 acrh3 acrh2 acrh1 acrh0 acrh w $001b alter. counter lsb r acrl7 acrl6 acrl5 acrl4 acrl3 acrl2 acrl1 acrl0 acrl w $001c reserved r w $001d analog control r chg atd2 atd1 icen cpie cpen isen acr w $001e analog status r cpf 000000 asr w cpfr $001f reserved r w unimplemented bits reserved bits figure 2-4. mc68HC05SB7 i/o registers $0010-$001f
august 27, 1998 general release specification mc68HC05SB7 memory motorola rev 2.1 2-5 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 sm-bus address r smad7 smad6 smad5 smad4 smad3 smad2 smad1 smadr w $0021 sm-bus freq. sel. r fd4 fd3 fd2 fd1 fd0 smfdr w $0022 sm-bus control r smen smien smsta smtx txak smux smcr w $0023 sm-bus status r smcf smaas smbb smal srw smif rxak smsr w smal clr smif clr $0024 sm-bus data r smd7 smd6 smd5 smd4 smd3 smd2 smd1 smd0 smdr w $0025 d/a register 0 r dac0 w d9 d8 d7 d6 d5 d4 d3 d2 $0026 d/a register 0 r dac0 w d1 d0 $0027 d/a register 1 r dac1 w d9 d8 d7 d6 d5 d4 d3 d2 $0028 d/a register 1 r dac1 w d1 d0 $0029 d/a register 2 r dac2 w d9 d8 d7 d6 d5 d4 d3 d2 $002a d/a register 2 r dac2 w d1 d0 $002b d/a register 3 r dac3 w d9 d8 d7 d6 d5 d4 d3 d2 $002c d/a register 3 r dac3 w d1 d0 $002d mux channel enable r pwm_i da3-e da2-e da1-e da0-e mcer w $002e reserved r w $002f reserved r w unimplemented bits reserved bits figure 2-5. mc68HC05SB7 i/o registers $0020-$002f addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $1ff0 cop register r 00000000 copr w copc figure 2-6. cop register (copr)
general release specification august 27, 1998 motorola memory mc68HC05SB7 2-6 rev 2.1 2.3 interrupt vector mapping the interrupt vectors are contained in the upper memory addresses above $1ff0 as shown in figure 2-2 . 2.4 rom there are a total of 6160 bytes of rom on chip. this includes 6144 bytes of user rom with locations $0600 through $1dff for the user program storage and another 16 bytes for user vectors at locations $1ff0 through $1fff. 2.5 ram the 224 addresses from $0040 to $011f serve as both the user ram and the stack ram. the stack begins at address $00c0 and proceeds down to $00ff. the stack pointer can access 64 locations from $00c0 to $00ff. using the stack area for data storage or temporary work locations requires care to prevent it from being over written due to stacking from an interrupt or subroutine call. the cpu uses ?e ram bytes to save all cpu register contents before processing an inter- rupt. during a subroutine call, the cpu uses two bytes to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. addr. register name $1ff0 cdet interrupt vector (msb) $1ff1 cdet interrupt vector (lsb) $1ff2 analog interrupt vector (msb) $1ff3 analog interrupt vector (lsb) $1ff4 sm-bus interrupt vector (msb) $1ff5 sm-bus interrupt vector (lsb) $1ff6 timer interrupt vector (msb) $1ff7 timer interrupt vector (lsb) $1ff8 ctimer interrupt vector (msb) $1ff9 ctimer interrupt vector (lsb) $1ffa external irq vector (msb) $1ffb external irq vector (lsb) $1ffc swi vector (msb) $1ffd swi vector (lsb) $1ffe reset vector (msb) $1fff reset vector(lsb) figure 2-7. mc68HC05SB7 interrupt vector mapping
august 27, 1998 general release specification mc68HC05SB7 central processing unit motorola rev 2.1 3-1 section 3 central processing unit the mc68HC05SB7 has an 8k-bytes memory map. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit
general release specification august 27, 1998 motorola central processing unit mc68HC05SB7 3-2 rev 2.1 3.2 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. 3.3 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register content to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary storage. the index register is not affected by a reset of the device. 3.4 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64($c0) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses ?e locations. 3.5 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched.
august 27, 1998 general release specification mc68HC05SB7 central processing unit motorola rev 2.1 3-3 normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.6.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.6.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.6.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g. 3.6.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero.
general release specification august 27, 1998 motorola central processing unit mc68HC05SB7 3-4 rev 2.1 3.6.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction.
august 27, 1998 general release specification mc68HC05SB7 interrupts motorola rev 2.1 4-1 section 4 interrupts an interrupt temporarily stops normal program execution to process a particular event. an interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. interrupt pro- cessing automatically saves the cpu registers on the stack and loads the pro- gram counter with a user-de?ed vector address. 4.1 interrupt vectors 1. copon enables the cop watchdog timer table 4-1 summarizes the reset and interrupt sources and vector assignments. table 4-1. reset/interrupt vector addresses function source control bit global hardware mask local software mask priority (1 = highest) vector address reset power-on logic reset pin low voltage reset illegal address reset 1 $1ffe?1fff cop watchdog copon 1 software interrupt (swi) user code same priority as instruction $1ffc?1ffd external interrupt (irq) irq /v pp pin i bit irqe bit 2 $1ffa?1ffb core timer interrupts tof bit rtif bit i bit tofe bit rtie bit 3 $1ff8?1ff9 programmable timer interrupts icf bit ocf bit tof bit i bit icie bit ocie bit toie bit 4 $1ff6?1ff7 sm-bus interrupt smif bit i bit smie bit 5 $1ff4?1ff5 analog interrupt cpf1 bit cpf2 bit i bit cpie bit 6 $1ff2?1ff3 current detect interrupt cif bit i bit cie bit 7 $1ff0?1ff1
general release specification august 27, 1998 motorola interrupts mc68HC05SB7 4-2 rev 2.1 note if more than one interrupt request is pending, the cpu fetches the vector of the higher priority interrupt ?st. a higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the i bit. 4.2 interrupt processing the cpu does the following actions to begin servicing an interrupt: stores the cpu registers on the stack in the order shown in figure 4-1 . sets the i bit in the condition code register to prevent further interrupts. loads the program counter with the contents of the appropriate interrupt vector locations as shown in table 4-1 . the return from interrupt (rti) instruction causes the cpu to recover its register contents from the stack as shown in figure 4-1 . the sequence of events caused by an interrupt are shown in the ?w chart in figure 4-2 . $0020 (bottom of ram) $0021 $00be $00bf $00c0 (bottom of stack) $00c1 $00c2 unstacking order ? n condition code register 5 1 n+1 accumulator 4 2 n+2 index register 3 3 n+3 program counter (high byte) 2 4 n+4 program counter (low byte) 1 5 y stacking $00fd order $00fe $00ff top of stack (ram) figure 4-1. interrupt stacking order
august 27, 1998 general release specification mc68HC05SB7 interrupts motorola rev 2.1 4-3 figure 4-2. interrupt flow chart no external interrupt? i bit set? from reset yes yes clear irq latch. no execute instruction. unstack ccr, a, x, pch, pcl. fetch next instruction. stack pcl, pch, x, a, ccr. set i bit. load pc with interrupt vector. core timer interrupt? yes no timer interrupt? yes no sm-bus interrupt? yes no analog interrupt? yes no swi instruction? yes no rti instruction? yes no cdet interrupt? yes no
general release specification august 27, 1998 motorola interrupts mc68HC05SB7 4-4 rev 2.1 4.3 software interrupt the software interrupt (swi) instruction causes a nonmaskable interrupt. 4.4 external interrupt the irq /v pp pin is the source that generates external interrupt. setting the i bit in the condition code register or clearing the irqe bit in the interrupt status and con- trol register disables this external interrupt. 4.4.1 irq /v pp pin an interrupt signal on the irq /v pp pin latches an external interrupt request. to help clean up slow edges, the input from the irq /v pp pin is processed by a schmitt trigger gate. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the irq status and control register (iscr). if the i bit is clear and the irqe bit is set, then the cpu begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 4-3 shows the logic for external interrupts. note if the irq /v pp pin is not in use, it should be connected to the v dd pin. the irq /v pp pin can be negative edge-triggered only or negative edge- and low- level-triggered. external interrupt sensitivity is programmed with the level bit. with the edge- and level-sensitive trigger option, a falling edge or a low level on the irq /v pp pin latches an external interrupt request. the edge- and level-sensi- tive trigger option allows connection to the irq /v pp pin of multiple wired-or inter- rupt sources. as long as any source is holding the irq /v pp low, an external interrupt request is present, and the cpu continues to execute the interrupt ser- vice routine. with the edge-sensitive-only trigger option, a falling edge on the irq /v pp pin latches an external interrupt request. a subsequent interrupt request can be latched only after the voltage level on the irq /v pp pin returns to a logic one and then falls again to logic zero.
august 27, 1998 general release specification mc68HC05SB7 interrupts motorola rev 2.1 4-5 figure 4-3. external interrupt logic 4.4.2 irq status and control register (iscr) the irq status and control register (iscr), shown in figure 4-4 , contains an external interrupt mask (irqe), an external interrupt ?g (irqf), and a ?g reset bit (irqr). unused bits will read as logic zeros. reset sets the irqe bit and clears all the other bits. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iscr r irqe vcoen level 0 irqf 0 0 0 $000d w irqr reset: 11000000 figure 4-4. irq status and control register (iscr) irq /v pp irq latch v dd rst irq vector fetch irq status/control register external interrupt request irqe irqf irqr internal data bus to bih & bil instruction processing r level v pp to user eprom and peprom
general release specification august 27, 1998 motorola interrupts mc68HC05SB7 4-6 rev 2.1 irqe ?external interrupt request enable this read/write bit enables external interrupts. reset sets the irqe bit. 1 = external interrupt processing enabled. 0 = external interrupt processing disabled. vcoen ?vco enable please refer to section on system clock. level ?external interrupt sensitivity this bit makes the external interrupt inputs level-triggered as well as edge-trig- gered. 1 = irq /v pp pin negative edge-triggered and low level-triggered. 0 = irq /v pp pin negative edge-triggered only. irqf ?external interrupt request flag the irq ?g is a clearable, read-only bit that is set when an external interrupt request is pending. reset clears the irqf bit. 1 = interrupt request pending. 0 = no interrupt request pending. the following condition set the irq ?g: an external interrupt signal on the irq /v pp pin. the following conditions clear the irq ?g: when the cpu fetches the interrupt vector. when a logic ? is written to the irqr bit. irqr ?interrupt request reset this write-only bit clears the irqf ?g bit and prevents redundant execution of interrupt routines. writing a logic one to irqr clears the irqf. writing a logic zero to irqr has no effect. irqr always reads as a logic zero. reset has no affect on irqr. 1 = clear irqf ?g bit. 0 = no effect. 4.5 core timer interrupts the core timer can generate the following interrupts: timer over?w interrupt. real-time interrupt. setting the i bit in the condition code register disables core timer interrupts. the controls and ?gs for these interrupts are in the core timer status and control reg- ister (ctscr) located at $0008.
august 27, 1998 general release specification mc68HC05SB7 interrupts motorola rev 2.1 4-7 4.5.1 core timer over?w interrupt an over?w interrupt request occurs if the core timer over?w ?g (tof) becomes set while the core timer over?w interrupt enable bit (tofe) is also set. the tof ?g bit can be reset by writing a logical one to the ctofr bit in the ctscr or by a reset of the device. 4.5.2 real-time interrupt a real-time interrupt request occurs if the real-time interrupt ?g (rtif) becomes set while the real-time interrupt enable bit (rtie) is also set. the rtif ?g bit can be reset by writing a logical one to the rtifr bit in the ctscr or by a reset of the device. 4.6 programmable timer interrupts the 16-bit programmable timer can generate an interrupt whenever the following events occur: input capture. output compare. timer counter over?w. setting the i bit in the condition code register disables timer interrupts. the con- trols for these interrupts are in the timer control register (tcr) located at $0012 and in the status bits are in the timer status register (tsr) located at $0013. 4.6.1 input capture interrupt an input capture interrupt occurs if the input capture ?g (icf) becomes set while the input capture interrupt enable bit (icie) is also set. the icf ?g bit is in the tsr; and the icie enable bit is located in the tcr. the icf ?g bit is cleared by a read of the tsr with the icf ?g bit is set; and then followed by a read of the lsb of the input capture register (icrl) or by reset. the icie enable bit is unaffected by reset. 4.6.2 output compare interrupt an output compare interrupt occurs if the output compare ?g (ocf) becomes set while the output compare interrupt enable bit (ocie) is also set. the ocf ?g bit is in the tsr and the ocie enable bit is in the tcr. the ocf ?g bit is cleared by a read of the tsr with the ocf ?g bit set; and then followed by an access to the lsb of the output compare register (ocrl) or by reset. the ocie enable bit is unaffected by reset. 4.6.3 timer over?w interrupt a timer over?w interrupt occurs if the timer over?w ?g (tof) becomes set while the timer over?w interrupt enable bit (toie) is also set. the tof ?g bit is in the tsr and the toie enable bit is in the tcr. the tof ?g bit is cleared by a
general release specification august 27, 1998 motorola interrupts mc68HC05SB7 4-8 rev 2.1 read of the tsr with the tof ?g bit set; and then followed by an access to the lsb of the timer registers (tmrl) or by reset. the toie enable bit is unaffected by reset. 4.7 sm-bus interrupt there is one sm-bus interrupt ?g that causes sm-bus interrupt whenever it is set and enabled. the interrupt ?gs is in the sm-bus status register (smsr) and the enable bit is in sm-bus control register (smcr). sm-bus interrupt can wake up mcu from wait mode. 4.8 analog interrupts the analog subsystem can generate the following interrupts: voltage on positive input of comparator is greater than the voltage on the negative input of comparator. trigger of the input capture interrupt from the programmable timer as described in section 4.6 above. setting the i bit in the condition code register disables analog subsystem inter- rupts. the controls for these interrupts are in the analog subsystem control regis- ter (acr) located at $001d and the status bits are in the analog subsystem status register (asr) located at $001e. 4.8.1 comparator input match interrupt a comparator input match interrupt occurs if the compare ?g bit (cpf) in the asr becomes set while the comparator interrupt enable bit (cpie) in the acr is also set. reset clears these bits. 4.8.2 input capture interrupt the analog subsystem can also generate an input capture interrupt through the programmable timer. the input capture can be triggered when there is a match in the input conditions for the voltage comparator. if comparator sets the cpf ?g bit in the asr and the input capture enable (icen) in the acr is set then an input capture will be performed by the programmable timer. if the icie enable bit in the tcr is also set then an input compare interrupt will occur. reset clears these bits. note in order for the analog subsystem to generate an interrupt using the input capture function of the programmable timer the icen enable bit in the acr and the icie enable bit in the tcr must both be set. 4.9 current detect interrupt the current sense ampli?r circuit can be con?ured to generate an interrupt once it detects a current passing through the current sensing resistor.
august 27, 1998 general release specification mc68HC05SB7 resets motorola rev 2.1 5-1 section 5 resets this section describes the ?e reset sources and how they initialize the mcu. a reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user de?ed reset vec- tor address. the following conditions produce a reset: initial power up of device (power on reset). a logic zero applied to the reset pin (external reset). timeout of the cop watchdog (cop reset). low voltage applied to the device (lvr reset). fetch of an opcode from an address not in the memory map (illegal address reset). figure 5-1 shows a block diagram of the reset sources and their interaction. figure 5-1. reset sources reset reset latch mcu internal register r copon cop watchdog power-on reset illegal address reset internal d internal clock s rst to cpu and lvren low voltage reset v dd 3-cycle clocked one-shot subsystems address bus 100k w v dd
general release specification august 27, 1998 motorola resets mc68HC05SB7 5-2 rev 2.1 5.1 power-on reset a positive transition on the v dd pin generates a power-on reset. the power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if the reset pin is at logic zero at the end of the multiple t cyc time, the mcu remains in the reset condition until the signal on the reset pin goes to a logic one. 5.2 external reset a logic zero applied to the reset pin for 1.5t cyc generates an external reset. this pin is connected to a schmitt trigger input gate to provide and upper and lower threshold voltage separated by a minimum amount of hysteresis. the exter- nal reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the internal rst signal that resets the cpu and peripher- als. the reset pin can also act as an open drain output. it will be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. this reset pulldown device will only be asserted for 3 - 4 cycles of the internal clock, f op , or as long as the internal reset source is asserted. when the external reset pin is asserted, the pulldown device will not be turned on. note do not connect the reset pin directly to v dd , as this may overload some power supply designs when the internal pulldown on the reset pin activates. 5.3 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the low voltage reset, and the illegal address detector. only the cop watchdog timer reset, low voltage reset and illegal address detec- tor will also assert the pulldown device on the reset pin for the duration of the reset function or 3 - 4 internal clock cycles, whichever is longer. 5.3.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabi- lize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active.
august 27, 1998 general release specification mc68HC05SB7 resets motorola rev 2.1 5-3 the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of the 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. por will not activate the pulldown device on the reset pin. v dd must drop below v por in order for the internal por circuit to detect the next rise of v dd . 5.3.2 computer operating properly (cop) reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic zero to the copc bit of the cop register at location $1ff0. copc ?cop clear copc is a write-only bit. periodically writing a logic zero to copc prevents the cop watchdog from resetting the mcu. reset clears the copc bit. 1 = no effect on system. 0 = reset cop watchdog timer. the cop watchdog reset will assert the pulldown device to pull the reset pin low for three to four clock cycles of the internal bus clock. after a por or reset, the cop watchdog is disabled. it is enabled b writing a logic ? to the copon bit in the miscellaneous control register (see figure 5-2 ). once enabled, the cop watchdog can only be disabled by a por or reset. copon ?cop on copon is a write-once bit. 1 = enables cop watchdog system. 0 = no effect on system. see section on core timer for detail on cop watchdog timeout periods. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 copr r 00000000 $1ff0 w copc reset: uuuuuuu0 u = unaffected by reset figure 5-2. cop watchdog register (copr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset figure 5-3. miscellaneous control register (mcr)
general release specification august 27, 1998 motorola resets mc68HC05SB7 5-4 rev 2.1 5.3.3 low voltage reset (lvr) the lvr activates the rst reset signal to reset the device when the voltage on the v dd pin falls below the lvr trip voltage. the lvr will assert the pulldown device to pull the reset pin low for three to four clock cycles of the internal bus clock. the low voltage reset circuit is enabled/disabled by the lvron bit in the miscellaneous control register (see figure 5-2 ). lvron ?lvr on this is a read/write bit to disable/enable the lvr circuit. 0 = low voltage reset circuit disabled. 1 = low voltage reset circuit enabled. this is the default setting at por or reset. 5.3.4 illegal address reset an opcode fetch from an address that is not in the eprom (locations $0600 $1dff and $1ff0 - $1fff) or the ram (locations $0030 ?$010f) generates an illegal address reset. the illegal address reset will assert the pulldown device to pull the reset pin low for 3 - 4 cycles of the internal bus clock. 5.4 reset states the following paragraphs describe how the various resets initialize the mcu. 5.4.1 cpu a reset has the following effects on the cpu: loads the stack pointer with $ff. sets the i bit in the condition code register, inhibiting interrupts. loads the program counter with the user de?ed reset vector from locations $1ffe and $1fff. clears the stop latch, enabling the cpu clock. clears the wait latch, bringing the cpu out of the wait mode. 5.4.2 i/o registers a reset has the following effects on i/o registers: clears bits in data direction registers con?uring pins as inputs: ddra7 ?ddra0 in ddra for port a. ddrb7 ?ddrb1 in ddra for port b. ddrc3?drc0 in ddra for port c. has no effect on port a, b or c data registers. sets the irqe bit in the interrupt status and control register.
august 27, 1998 general release specification mc68HC05SB7 resets motorola rev 2.1 5-5 5.4.3 core timer a reset has the following effects on the core timer: clears the core timer counter register (ctcr). clears the core timer interrupt ?g and enable bits in the core timer status and control register (ctscr). sets the real-time interrupt rate selection bits (rt0, rt1) such that the device will start with the longest real-time interrupt and cop timeout delays. 5.4.4 cop watchdog a reset clears the cop watchdog timeout counter. 5.4.5 16-bit programmable timer a reset has the following effects on the 16-bit programmable timer: initializes the timer counter registers (tmrh, tmrl) to a value of $fffc. initializes the alternate timer counter registers (acrh, acrl) to a value of $fffc. clears all the interrupt enables and the output level bit (olvl) in the timer control register (tcr). does not affect the input capture edge bit (iedg) in the tcr. does not affect the interrupt ?gs in the timer status register (tsr). does not affect the input capture registers (icrh, icrl). does not affect the output compare registers (ocrh, ocrl). 5.4.6 sm-bus serial interface a reset has the following effects on the sm-bus serial interface: clears all bits in the address register (smadr) and those unimplemented bit locations are not affected. clears all bits in the frequency divider register (smfdr) and those unimplemented bit locations are not affected. clears all bits in control register (smcr) and those unimplemented bit locations are not affected. sets smcf & rxak bits and clears other bits and those unimplemented bit locations are not affected. does not affect the contents of the data i/o register (smdr).
general release specification august 27, 1998 motorola resets mc68HC05SB7 5-6 rev 2.1 a reset therefore disables the sm-bus and leaves the shared port a pins as gen- eral i/o. any pending interrupt ?g is cleared and the sm-bus interrupt is dis- abled. also the clock rate defaults to the fastest rate. 5.4.7 analog subsystem a reset has the following effects on the analog subsystem: clears all the bits in the multiplex registers (amux1, amux2) bits except the hold switch bit (hold) which is set. clears all the bits in the analog control register (acr). clears all the bits in the analog status register (asr). a reset therefore connects the negative input of comparator to the channel selec- tion bus, which is switched to v ss . the comparator is set up as non-inverting (a higher positive voltage on the positive input results in a positive output) and both are powered down. the current source and discharge device on the cap pin is also disabled and powered down. any analog subsystem interrupt ?gs are cleared and the interrupts are disabled.
august 27, 1998 general release specification mc68HC05SB7 low power modes motorola rev 2.1 6-1 section 6 low power modes there are four modes of operation that reduce power consumption: stop mode wait mode data retention mode slow mode figure 6-1 shows the sequence of events in stop and wait modes.
general release specification august 27, 1998 motorola low power modes mc68HC05SB7 6-2 rev 2.1 figure 6-1. stop and wait flowchart stop clear i bit in ccr. set irqe bit in iscr. clear ctof, rtif, ctofe, and rtie bits in tscr. disable oscillator external reset? external interrupt? no no turn on oscillator. reset stabilization delay timer. yes yes end of stabilization delay? yes no wait turn on cpu clock. 1. load pc with reset vector or 2. service interrupt. a. save cpu registers on stack. b. set i bit in ccr. c. load pc with interrupt vector. clear icf, ocf and tof bits in tsr. clear icie, ocie and toie bits in tcr. clear i bit in ccr. set irqe bit in iscr. turn off cpu clock. keep other module clocks active. no external reset? yes no interrupt? yes cdet no external interrupt? yes no prog. interrupt? yes timer no sm-bus interrupt? yes no yes no cop reset? yes interrupt? analog core interrupt? timer yes no
august 27, 1998 general release specification mc68HC05SB7 low power modes motorola rev 2.1 6-3 6.1 stop mode the stop instruction puts the mcu in a mode with the lowest power consumption and has the following affect on the mcu: turns off the cpu clock and all internal clocks by stopping the internal oscillator. the stopped clocks turn off the cop watchdog, the core timer, the programmable timer, the analog subsystem and the sm-bus interface. removes any pending core timer interrupts by clearing the core timer interrupt ?gs (ctof, rtif) in the core timer status and control register (ctscr). disables any further core timer interrupts by clearing the core timer interrupt enable bits (ctofe, rtie) in the ctscr. removes any pending programmable timer interrupts by clearing the timer interrupt ?gs (icf, ocf and tof) in the timer status register (tsr). disables any further programmable timer interrupts by clearing the timer interrupt enable bits (icie, ocie and toie) in the timer control register (tcr). enables external interrupts via the irq /v pp pin by setting the irqe bit in the irq status and control register (iscr). enables interrupts in general by clearing the i bit in the condition code register. the stop instruction does not affect any other bits, registers or i/o lines. the following conditions bring the mcu out of stop mode: an external interrupt signal on the irq /v pp pin ?a high to low transition on the irq /v pp pin loads the program counter with the contents of locations $1ffa and $1ffb. external reset ?a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. when the mcu exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles. if an external interrupt brings the mcu out of stop mode after an active edge occurred on the pc3/tcap during the stop mode, the icf ?g becomes set. an external interrupt also latches the value of the timer registers into the input cap- ture registers. if an external reset brings the mcu out of the stop mode after an active edge occurred on the pc3/tcap pin during the stop mode, the icf ?g does not become set. an external reset has no effect on the input capture registers.
general release specification august 27, 1998 motorola low power modes mc68HC05SB7 6-4 rev 2.1 6.2 wait mode the wait instruction puts the mcu in a low power wait mode which consumes more power than the stop mode. the wait mode and has the following affects on the mcu: enables interrupts by clearing the i bit in the condition code register. enables external interrupts by setting the irqe bit in the irq status and control register. stops the cpu clock which drives the address and data buses, but allows the internal oscillator and its clock to continue to run and drive the core timer, programmable timer, analog subsystem and sm-bus. the wait instruction does not affect any other bits, registers or i/o lines. the following conditions restart the cpu clock and bring the mcu out of the wait mode: an external interrupt signal on the irq /v pp pin ?a high to low transition on the irq /v pp pin loads the program counter with the contents of locations $1ffa and $1ffb. a programmable timer interrupt ?a programmable timer interrupt driven by an input capture, output compare or timer over?w loads the program counter with the contents of locations $1ff6 and $1ff7. an sm-bus interrupt ?an sm-bus interrupt driven by the completion of transmitted or received 8-bit data loads the program counter with the contents of locations $1ff4 and $1ff5. an analog subsystem interrupt ?an analog subsystem interrupt driven by a voltage comparison loads the program counter with the contents of locations $1ff2 and $1ff3. a core timer interrupt ?a core timer over?w or a real time interrupt loads the program counter with the contents of locations $1ff0 and $1ff1. a cop watchdog reset ?a timeout of the cop watchdog resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. software can enable real time interrupts so that the mcu can periodically exit the wait mode to reset the cop watchdog. external reset ?a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. 6.3 data-retention mode in the data retention mode, the mcu retains ram contents and cpu register con- tents at v dd voltages as low as 2.0 vdc. the data retention feature allows the mcu to remain in a low power consumption state during which it retains data, but the cpu cannot execute instructions.
august 27, 1998 general release specification mc68HC05SB7 low power modes motorola rev 2.1 6-5 to put the mcu in the data retention mode: 1. drive the reset pin to a logic zero. 2. lower the v dd voltage. the reset pin must remain low continuously during data retention mode. to take the mcu out of the data retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to a logic one. 6.4 slow mode the slow mode feature permits a slow down of all the internal operations and thus reduces power consumption. it is particularly useful while going to the wait mode. slow mode is enabled by setting the sclk bit in the miscellaneous control register ($0b). sclk ?slow clock setting this bit to one will slow down the internal oscillator. setting this bit to zero the system will run at the nominal bus speed (f osc /2). this bit is cleared during power-on or external reset. 1 = slow clock selected: internal operating frequency, f op =f bus =f osc /1600. 0 = normal clock selected: internal operating frequency, f op =f bus =f osc /2. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset figure 6-2. miscellaneous control register (mcr)
general release specification august 27, 1998 motorola low power modes mc68HC05SB7 6-6 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 input/output ports motorola rev 2.1 7-1 section 7 input/output ports in normal operating mode there are 19 bidirectional i/o lines arranged as three i/ o ports (port a, b and c). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). all port i/o pins can sink a current of 5ma when programmed as outputs. 7.1 parallel ports port a, b and c are bidirectional ports. each port pin is controlled by the corre- sponding bits in a data direction register and a data register as shown in figure 7- 1 . figure 7-1. port i/o circuitry table 7-1. i/o pin functions r/w ddr i/o pin functions 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. i/o pin read data write data data register bit internal hc05 data bus reset (rst) read/write ddr data direction register bit output
general release specification august 27, 1998 motorola input/output ports mc68HC05SB7 7-2 rev 2.1 7.1.1 port data registers each port i/o pin has a corresponding bit in the port data register. when a port i/ o pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. all port i/o pins can sink a current of 5ma when programmed as outputs. when a port pin is programmed as an input, any read of the port data register will return the logic state of the corresponding i/o pin. 7.1.2 port data direction registers each port i/o pin may be programmed as an input by clearing the corresponding bit in the ddr, or programmed as an output by setting the corresponding bit in the ddr. note a ?litch can be generated on an i/o pin when changing it from an input to an output unless the data register is ?st preconditioned to the desired state before changing the corresponding ddr bit from a ? to a ?? therefore, write data to the i/o port data register before writing a ? to the corresponding data direction register. 7.2 port a port a is an 8-bit bidirectional port with pins shared with the pwm outputs and sm-bus serial i/os. the port a data register is at address $0000 and the data direction register is at address $0004. 7.3 port b port b is a 7-bit birdirectional port with pins shared with a/d converter inputs, cur- rent detect outputs, and the 16-bit timer tcap input. the port b data register is at address $0001 and the data direction register is at address $0005. when selected by mask option, port pins pb2 and pb3 becomes osc1 and osc2 respectively. 7.4 port c port c is a 4-bit bidirectional port. the port c data register is at address $0002 and the data direction register is at address $0006.
august 27, 1998 general release specification mc68HC05SB7 system clock motorola rev 2.1 8-1 section 8 system clock this section describes the system clock options for the mc68HC05SB7. 8.1 clock sources the internal operating clock of the mc68HC05SB7 is derived from two possible clock sources: external oscillator input via the osc1 and osc2 pins - this is enabled by a mask option on the mc68HC05SB7. (on the mc68hc705sb7, the oscs bit in the mask option register enables/disables external osc input option.) internal vco generated. figure 8-1. mc68HC05SB7 input clock source vco va0 va1 va2 va3 va4 vcoen sclk mux osc2 i/o port ?2 osc1 osc oscs f op
general release specification august 27, 1998 motorola system clock mc68HC05SB7 8-2 rev 2.1 the clock source is selected by the vcoen bit in the irq status and control reg- ister at $0d. table 8-1 shows a summary of the clock source selection. vcoen ?vco enable 1 = internal vco is used as clock source for the mcu. this is the default setting after a reset. 0 = external osc is used as clock source for the mcu. if external osc is disabled (mask option or mor in mc68hc705sb7), the internal vco is used as clock source. after a por or reset, the internal vco is selected as the default clock source. . note the user must ensure that the oscillators are stable (4096 clock cycles minimum) if switching between internal and external oscillators. 8.2 vco clock speed 8.2.1 vco slow mode the internal vco has two operating modes: normal mode and slow mode. in normal mode, the vco frequency ranges from 1.5mhz to 5.8mhz. in slow mode, the vco frequency ranges from 500hz to 4khz. this clock speed option is selected by setting the sclk bit in the miscellaneous register at $0b. the default setting at reset is normal mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iscr r irqe vcoen level 0 irqf 0 0 0 $000d w irqr reset: 11000000 figure 8-2. irq status and control register (iscr) table 8-1. clock source selection external osc enabled (mask option) internal vco enabled clock source selected disabled (oscs=0 in mc68hc705sb7) don? care (vcoen=x) internal enabled (oscs=1 in mc68hc705sb7) disabled (vcoen=0) external enabled (oscs=1 in mc68hc705sb7) enabled (vcoen=1) internal
august 27, 1998 general release specification mc68HC05SB7 system clock motorola rev 2.1 8-3 sclk ?slow clock 1 = slow clock selected ?vco frequency: 500hz to 4khz. 0 = normal clock selected ?vco frequency: 1.5mhz to 5.8mhz. note due to process variations, operating voltages, and temperature requirements, the quoted vco frequencies are typical limits, and should be treated as references only. it is the users responsibility to ensure that the resulting internal operating frequency meets users requirement by setting the appropriate value in the vco adjust register. see below. 8.2.2 setting the vco speed the speed of the internal vco can be adjusted by con?uring ?e bits in the vco adjust register (var) as shown in figure 8-4 . setting var=11111 will select the vco minimum frequency, and var=00000 will select the maximum frequency. on reset, var=10000, which selects the mid-frequency. for normal mode, when var=10000, vco frequency is typically 2khz. for slow mode, when var=10000, vco frequency is typically 3.4mhz. the vco minimum and maximum frequencies are available preprogrammed as two 16-bit values in the personality eprom (peprom). bit locations $00 to $0f holds the minimum value, and $10 to $1f holds the maximum value. see section on personality eprom for further details. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset figure 8-3. miscellaneous control register (mcr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 var r 0 0 0 va4 va3 va2 va1 va0 $000c w reset: 00010000 u = unaffected by reset figure 8-4. vco adjust register (var)
general release specification august 27, 1998 motorola system clock mc68HC05SB7 8-4 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 core timer motorola rev 2.1 9-1 section 9 core timer this section describes the operation of the core timer and the computer operating properly (cop) watchdog timer. figure 9-1 shows a block diagram of the core timer. figure 9-1. core timer block diagram bits 0? of 15-stage internal data bus ripple (count-up) counter cop register rti rate select ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 s r q reset cop watchdog reset power-on reset f op ? 1024 ctof rtif ctofe rtie ctofr rtifr rt1 rt0 core timer request interrupt core timer status/control register copc ? 2 ? 2 ? 2 reset core timer counter register overflow reset ? 4 osc1 (f osc ) ? 2 internal clock (f op ) $0009 $0008 $1ff0 f op ? 2 14 f op ? 2 17 f op ? 2 16 f op ? 2 15
general release specification august 27, 1998 motorola core timer mc68HC05SB7 9-2 rev 2.1 9.1 core timer status and control register the read/write core timer status and control register contains the interrupt ?g bits, interrupt enable bits, interrupt ?g bit resets, and the rate selects for the real time interrupt as shown in figure 9-2 . ctof ?core timer over?w flag this read only ?g becomes set when the ?st eight stages of the core timer counter roll over from $ff to $00. the ctof ?g bit generates a timer over?w interrupt request if ctofe is also set. the ctof ?g bit is cleared by writing a logic one to the ctofr bit. writing to ctof has no effect. reset clears ctof. 1 = over?w in core timer has occurred. 0 = no over?w of core timer since ctof last cleared. rtif ?real time interrupt flag this read only ?g becomes set when the selected rti output becomes active. rtif generates a real time interrupt request if rtie is also set. the rtif enable bit is cleared by writing a logic one to the rtifr bit. writing to rtif has no effect. reset clears rtif. 1 = over?w in real time counter has occurred. 0 = no over?w of real time counter since rtif last cleared. ctofe ?core timer over?w interrupt enable this read/write bit enables core timer over?w interrupts. reset clears ctofe. 1 = core timer over?w interrupts enabled. 0 = core timer over?w interrupts disabled. rtie ?real-time interrupt enable this read/write bit enables real time interrupts. reset clears rtie. 1 = real-time interrupts enabled. 0 = real-time interrupts disabled. ctofr ?core timer over?w flag reset writing a logic one to this write only bit clears the ctof bit. ctofr always reads as a logic zero. reset does not affect ctofr. 1 = clear ctof ?g bit. 0 = no effect on ctof ?g bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctscr r ctof rtif ctofe rtie 00 rt1 rt0 $0008 w ctofr rtifr reset: 00000011 figure 9-2. core timer status and control register (ctscr)
august 27, 1998 general release specification mc68HC05SB7 core timer motorola rev 2.1 9-3 rtifr ?real-time interrupt flag reset writing a logic one to this write only bit clears the rtif bit. rtifr always reads as a logic zero. reset does not affect rtifr. 1 = clear rtif ?g bit. 0 = no effect on rtif ?g bit. rt1, rt0 ?real-time interrupt select bits 1 and 0 these read/write bits select one of four real time interrupt rates, as shown in table 9-1 . because the selected rti output drives the cop watchdog, chang- ing the real time interrupt rate also changes the counting rate of the cop watchdog. reset sets rt1 and rt0, selecting the longest cop timeout period and real-time interrupt period. note changing rt1 and rt0 when a cop timeout is imminent or uncertain may cause a real time interrupt request to be missed or an additional real time interrupt request to be generated. therefore, the cop timer should be cleared (by writing a just before changing rt1 and rt0. 9.2 core timer counter register (ctcr) a 15-stage ripple counter is the basis of the core timer. the value of the ?st eight stages is readable at any time from the read only timer counter register as shown in figure 9-2 . table 9-1. core timer interrupt rates and cop timeout selection timer overflow interrupt (tof) period (f op ? 2 10 ) rt1 rt0 rti rate real-time interrupt (rti) period minimum cop timeout period (7 or 8 rti periods) f op = 2.1 mhz f op = 1.0 mhz f op = 2.1 mhz f op = 1.0 mhz f op = 2.1 mhz f op = 1.0 mhz 488 m s 1024 m s 00f op ? 2 14 7.81 ms 16.4 ms 54.7 ms 114 ms 01f op ? 2 15 15.6 ms 32.8 ms 109 ms 229 ms 10f op ? 2 16 31.3 ms 65.5 ms 219 ms 458 ms 11f op ? 2 17 62.5 ms 131 ms 438 ms 916 ms bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctcr r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 $0009 w reset: 00000000 figure 9-3. core timer counter register (ctcr)
general release specification august 27, 1998 motorola core timer mc68HC05SB7 9-4 rev 2.1 power on clears the entire counter chain and begins clocking the counter. after the startup delay (16 or 4064 internal clock cycles) the power on reset circuit is released, clearing the counter again and allowing the mcu to come out of reset. each count of the timer counter register takes eight oscillator cycles or four cycles of the internal clock. a timer over?w function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. 9.3 cop watchdog four counter stages at the end of the core timer make up the computer operating properly (cop) watchdog. the cop watchdog timeout period is shown in table 9- 1 . a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic ??to the copc bit of the cop register at location $1ff0. copc ?cop clear copc is a write-only bit. periodically writing a logic zero to copc prevents the cop watchdog from resetting the mcu. reset clears the copc bit. 1 = no effect on system. 0 = reset cop watchdog timer. the cop watchdog reset will assert the pulldown device to pull the reset pin low for three to four clock cycles of the internal bus clock. after a por or reset, the cop watchdog is disabled. it is enabled b writing a logic ? to the copon bit in the miscellaneous control register (see figure 9-5 ). once enabled, the cop watchdog can only be disabled by a por or reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 copr r 00000000 $1ff0 w copc reset: uuuuuuu0 u = unaffected by reset figure 9-4. cop watchdog register (copr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset figure 9-5. miscellaneous control register (mcr)
august 27, 1998 general release specification mc68HC05SB7 core timer motorola rev 2.1 9-5 copon ?cop on copon is a write-once bit. 1 = enables cop watchdog system. 0 = no effect on system. note if the voltage on the irq /v pp pin exceeds 2 v dd , the cop watchdog is disabled, and remains disabled until the irq /v pp voltage falls below 2 v dd . 9.4 core timer during wait mode the cpu clock halts during the wait mode, but the timer remains active. if the interrupts are enabled, the timer interrupt will cause the processor to exit the wait mode. 9.5 core timer during stop mode the core timer is cleared when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will resume, fol- lowed by 4064 cycles internal processor stabilization delay. the timer is then cleared and operation resumes.
general release specification august 27, 1998 motorola core timer mc68HC05SB7 9-6 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-1 section 10 16-bit timer the mc68HC05SB7 mcu contains a 16-bit programmable timer with an input capture function and an output compare function. figure 10-1 shows a block diagram of the 16-bit programmable timer. figure 10-1. programmable timer block diagram iedg olvl icie ocie toie tmrh ($0018) tmrl ($0019) 16-bit counter ? 4 internal (f osc ? 2) timer control register timer request overflow (tof) reset clock interrupt acrh ($001a) acrl ($001b) 16-bit comparator ocrh ($0016) ocrl ($0017) pb1 tcap edge select & detect icf ocf tof timer status register iedg icf ocf olvl $0012 $0013 internal data bus logic input select mux cpf flag icen (bit 4 of $1d) bit icrh ($0014) icrl ($0015) d c q tcmp tcsel (bit 2 of $0b) scl of smbus (from analog subsystem)
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-2 rev 2.1 the basis of the capture/compare timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. the counter is the timing ref- erence for the input capture and output compare functions. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. because of the 16-bit timer architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers. each register pair contains the high and low byte of that function. generally, accessing the low byte of a spe- ci? timer function allows full control of that function; however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. because the counter is 16 bits long and preceded by a ?ed divide-by-four pres- caler, the counter rolls over every 262,144 internal clock cycles. timer resolution with a 4 mhz crystal oscillator is 2 microsecond/count. the interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (tcr) located at $0012 and the status of the interrupt ?gs can be read from the timer status register (tsr) located at $0013. 10.1 timer registers (tmrh, tmrl) the functional block diagram of the 16-bit free-running timer counter and timer registers is shown in figure 10-2 . the timer registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 10-2. programmable timer block diagram toie tmrh ($0018) tmr lsb 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request overflow (tof) reset clock interrupt tmrl ($0019) tof timer status reg. $0012 $0013 internal ($fffc) data read tmrh read tmrl read latch bus
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-3 the timer registers (tmrh, tmrl) shown in figure 10-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the timer registers has no effect. reset of the device presets the timer counter to $fffc. the tmrl latch is a transparent read of the lsb until the a read of the tmrh takes place. a read of the tmrh latches the lsb into the tmrl location until the tmrl is again read. the latched value remains ?ed even if multiple reads of the tmrh take place before the next read of the tmrl. therefore, when reading the msb of the timer at tmrh the lsb of the timer at tmrl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is sixteen bits and preceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). when the free-running counter rolls over from $ffff to $0000, the timer over?w ?g bit (tof) is set in the tsr. when the tof is set, it can generate an interrupt if the timer over?w interrupt enable bit (toie) is also set in the tcr. the tof ?g bit can only be reset by reading the tmrl after reading the tsr. other than clearing any possible tof ?gs, reading the tmrh and tmrl in any order or any number of times does not have any effect on the 16-bit free-running counter. note to prevent interrupts from occurring between readings of the tmrh and tmrl, set the i bit in the condition code register (ccr) before reading tmrh and clear the i bit after reading tmrl. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmrh r tmrh7 tmrh6 tmrh5 tmrh4 tmrh3 tmrh2 tmrh1 tmrh0 $0018 w reset: 11111111 tmrl r tmrl7 tmrl6 tmrl5 tmrl4 tmrl3 tmrl2 tmrl1 tmrl0 $0019 w reset: 11111100 figure 10-3. programmable timer registers (tmrh, tmrl)
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-4 rev 2.1 10.2 alternate counter registers (acrh, acrl) the functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in figure 10-4 . the alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the tof ?g bit and timer interrupts. the alternate counter registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 10-4. alternate counter block diagram the alternate counter registers (acrh, acrl) shown in figure 10-5 are read- only locations which contain the current high and low bytes of the 16-bit free-run- ning counter. writing to the alternate counter registers has no effect. reset of the device presets the timer counter to $fffc. the acrl latch is a transparent read of the lsb until the a read of the acrh takes place. a read of the acrh latches the lsb into the acrl location until the acrl is again read. the latched value remains ?ed even if multiple reads of the acrh take place before the next read of the acrl. therefore, when reading the msb of the timer at acrh the lsb of the timer at acrl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is sixteen bits and preceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). reading the acrh and acrl in any order or any number of times does not have any effect on the 16-bit free-running counter or the tof ?g bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acrh r acrh7 acrh6 acrh5 acrh4 acrh3 acrh2 acrh1 acrh0 $001a w reset: 11111111 acrl r acrl7 acrl6 acrl5 acrl4 acrl3 acrl2 acrl1 acrl0 $001b w reset: 11111100 figure 10-5. alternate counter registers (acrh, acrl) acrh ($001a) tmr lsb 16-bit counter ? 4 internal (f osc ? 2) reset clock acrl ($001b) internal ($fffc) data read acrh read acrl read latch bus
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-5 note to prevent interrupts from occurring between readings of the acrh and acrl, set the i bit in the condition code register (ccr) before reading acrh and clear the i bit after reading acrl. 10.3 input capture registers figure 10-6. timer input capture block diagram the input capture function is a means to record the time at which an event occurs. the source of the event can be selected from the following: external input via the pb1 pin cpf ?g from the voltage comparator in the analog subsystem scl signal from the smbus the input capture source is selected by the tcsel and icen bits. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 figure 10-7. miscellaneous control register (mcr) icie icrh ($0014) 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request input capture (icf) reset clock interrupt icrl ($0015) icf timer status reg. $0012 $0013 internal ($fffc) data read icrh read icrl latch bus iedg edge select & detect logic iedg pb1 tcap input select mux cpf flag icen (bit 4 of $1d) bit internal data bus tcsel (bit 2 of $0b) scl of smbus
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-6 rev 2.1 when the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input cap- ture registers as shown in figure 10-6 . latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. latching the counter val- ues at successive edges of opposite polarity measures the pulse width of the sig- nal. the input capture registers are made up of two 8-bit read-only registers (icrh, icrl) as shown in figure 10-9 . the input capture edge detector contains a schmitt trigger to improve noise immunity. the edge that triggers the counter transfer is de?ed by the input edge bit (iedg) in the tcr. reset does not affect the contents of the input capture registers. the result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acr r chg atd2 atd1 icen cpie cpen isen $001d w reset: 00000000 figure 10-8. analog control register (acr) table 10-1. 16-bit timer input capture source tcsel icen selected tcap source 0 0 external tcap via pb1 0 1 cpf from analog subsystem 1 0 scl from smbus 1 1 scl from smbus bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icrh r icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 $0014 w reset: uuuuuuuu icrl r icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 $0015 w reset: uuuuuuuu u = unaffected by reset figure 10-9. input capture registers (icrh, icrl)
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-7 reading the icrh inhibits further captures until the icrl is also read. reading the icrl after reading the timer status register (tsr) clears the icf ?g bit. does not inhibit transfer of the free-running counter. there is no con?ct between read- ing the icrl and transfers from the free-running timer counters. the input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. note to prevent interrupts from occurring between readings of the icrh and icrl, set the i bit in the condition code register (ccr) before reading icrh and clear the i bit after reading icrl. 10.4 output compare registers figure 10-10. timer output compare block diagram the output compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in figure 10-10 . software writes the selected value into the output compare registers. on every fourth inter- nal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. when a match occurs, the timer transfers the output level (olvl) from the timer control register (tcr) to the tcmp. ocie ocrh ($0016) 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request output compare reset clock interrupt ocrl ($0017) ocf timer status reg. $0012 $0013 internal ($fffc) data r/w ocrh r/w ocrl bus olvl edge select detect logic olvl 16-bit comparator (ocf) tcmp
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-8 rev 2.1 software can use the output compare register to measure time periods, to gener- ate timing delays, or to generate a pulse of speci? duration or a pulse train of speci? frequency and duty cycle on the tcmp. the planned action on the tcmp depends on the value stored in the olvl bit in the tcr, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in figure 10-3 . these registers are read/write bits and are unaffected by reset. writing to the ocrh before writing to the ocrl inhibits timer compares until the ocrl is written. reading or writing to the ocrl after reading the tsr will clear the output compare ?g bit (ocf). the output compare olvl state will be clocked to its output latch regardless of the state of the ocf. to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use the following procedure: 1. disable interrupts by setting the i bit in the condition code register. 2. write to the ocrh. compares are now inhibited until ocrl is written. 3. read the tsr to arm the ocf for clearing. 4. enable the output compare registers by writing to the ocrl. this also clears the ocf ?g bit in the tsr. 5. enable interrupts by clearing the i bit in the condition code register. a software example of this procedure is shown below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrh r ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 $0016 w reset: uuuuuuuu ocrl r ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 $0017 w reset: uuuuuuuu u = unaffected by reset figure 10-11. output compare registers (ocrh, ocrl) 9b ... ... b7 b6 bf ... ... 9a 16 13 17 sei ... ... sta lda stx ... ... cli ocrh tsr ocrl disable interrupts ..... ..... inhibit output compare arm ocf flag for clearing ready for next compare, ocf cleared ..... ..... enable interrupts
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-9 10.5 timer control register (tcr) the timer control register is shown in figure 10-12 performs the following func- tions: enables input capture interrupts. enables output compare interrupts. enables timer over?w interrupts. control the active edge polarity of the tcap signal. controls the active level of the tcmp output. reset clears all the bits in the tcr with the exception of the iedg bit which is unaffected. icie - input capture interrupt enable this read/write bit enables interrupts caused by an active signal on the pb1/ tcap pin or from cpf ?g bit of the analog subsystem voltage comparator. reset clears the icie bit. 1 = input capture interrupts enabled. 0 = input capture interrupts disabled. ocie - output compare interrupt enable this read/write bit enables interrupts caused by an active signal on the tcmp pin. reset clears the ocie bit. 1 = output compare interrupts enabled. 0 = output compare interrupts disabled. toie - timer overflow interrupt enable this read/write bit enables interrupts caused by a timer over?w. reset clears the toie bit. 1 = timer over?w interrupts enabled. 0 = timer over?w interrupts disabled. iedg - input capture edge select the state of this read/write bit determines whether a positive or negative transi- tion on the tcap pin or the cpf ?g bit of voltage comparator in the analog subsystem triggers a transfer of the contents of the timer register to the input capture register. reset has no effect on the iedg bit. 1 = positive edge (low to high transition) triggers input capture. 0 = negative edge (high to low transition) triggers input capture. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr r icie ocie toie 000 iedg olvl $0012 w reset: 000000 unaffected 0 figure 10-12. timer control register (tcr)
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-10 rev 2.1 olvl - output compare output level select the state of this read/write bit determines whether a logic one or a logic zero appears on the tcmp when a successful output compare occurs. reset clears the olvl bit. 1 = tcmp goes high on output compare. 0 = tcmp goes low on output compare. 10.6 timer status register (tsr) the timer status register (tsr) shown in figure 10-13 contains ?gs for the fol- lowing events: an active signal on the pb1/tcap pin or the cpf ?g bit of voltage comparator in the analog subsystem, transferring the contents of the timer registers to the input capture registers. a match between the 16-bit counter and the output compare registers, transferring the olvl bit to the tcmp. an over?w of the timer registers from $ffff to $0000. writing to any of the bits in the tsr has no effect. reset does not change the state of any of the ?g bits in the tsr. icf - input capture flag the icf bit is automatically set when an edge of the selected polarity occurs on the pb1/tcap pin. clear the icf bit by reading the timer status register with the icf set, and then reading the low byte (icrl, $0015) of the input capture registers. reset has no effect on icf. ocf - output compare flag the ocf bit is automatically set when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with the ocf set, and then accessing the low byte (ocrl, $0017) of the output compare registers. reset has no effect on ocf. tof - timer overflow flag the tof bit is automatically set when the 16-bit timer counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with the tof set, and then accessing the low byte (tmrl, $0019) of the timer registers. reset has no effect on tof. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tsrricfocftof00000 $0013 w reset: u u u 00000 u = unaffected by reset figure 10-13. timer status registers (tsr)
august 27, 1998 general release specification mc68HC05SB7 16-bit timer motorola rev 2.1 10-11 10.7 timer operation during wait mode during wait mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the mcu out of the wait mode. 10.8 timer operation during stop mode when the mcu enters the stop mode the free-running counter stops counting (the internal processor clock is stopped). it remains at that particular count value until the stop mode is exited by applying a low signal to the irq pin, at which time the counter resumes from its stopped value as if nothing had happened. if stop mode is exited via an external reset (logic low applied to the reset pin) the counter is forced to $fffc. if a valid input capture edge occurs at the pb1/tcap pin during the stop mode the input capture detect circuitry will be armed. this action does not set any ?gs or ?ake up the mcu, but when the mcu does ?ake up there will be an active input capture ?g (and data) from the ?st valid edge. if the stop mode is exited by an external reset, no input capture ?g or data will be present even if a valid input capture edge was detected during the stop mode.
general release specification august 27, 1998 motorola 16-bit timer mc68HC05SB7 10-12 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 pulse width modulator motorola rev 2.1 11-1 section 11 pulse width modulator the pwm subsystem contains four 10-bit pwm channels, which can be used as independent d/a converters. figure 11-1 shows the block diagram for the pulse width modulator, with channel 0 in details. figure 11-1. pwm block diagram the pwm cycle time is 2048 times the mcu internal processor clock (f op or f bus ). duty cycle of the pwm outputs can be programmed by the corresponding d/a data registers (dac0-dac3). zero detector internal bus 10-bit d/a 0 data register 10-bit d/a 0 data register buffer comparator 10-bit counter d/a 0 multiplexer pwm0 pin s r latch f op ? 2 channel 0 to channel 1 to channel 2 to channel 3
general release specification august 27, 1998 motorola pulse width modulator mc68HC05SB7 11-2 rev 2.1 11.1 d/a data registers (dac0-dac3) each pwm channel is programmed with a 10-bit data, in two 8-bit registers. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac0 r $0025 w d9 d8 d7 d6 d5 d4 d3 d2 reset: 00000000 figure 11-2. d/a data register 0 (dac0) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac0 r $0026 w d1 d0 reset: 00000000 figure 11-3. d/a data register 0 (dac0) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac1 r $0027 w d9 d8 d7 d6 d5 d4 d3 d2 reset: 00000000 figure 11-4. d/a data register 1 (dac1) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac1 r $0028 w d1 d0 reset: 00000000 figure 11-5. d/a data register 1 (dac1) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac2 r $0029 w d9 d8 d7 d6 d5 d4 d3 d2 reset: 00000000 figure 11-6. d/a data register 2 (dac2) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac2 r $002a w d1 d0 reset: 00000000 figure 11-7. d/a data register 2 (dac2) (lsb)
august 27, 1998 general release specification mc68HC05SB7 pulse width modulator motorola rev 2.1 11-3 a value of $0000 loaded into these registers results in a continuously low output on the corresponding pwm output pin. a value of $0200 results in a 50% duty cycle output, and so on. the maximum value, $03ff corresponds to an output which is at ? for 1023/1024 of the cycle. figure 11-10. pwm output waveform examples a new value written to the a d/a register pair will not be effective until the end of the current pwm period. this provides a monotonic change of the dc component of the output without overshoots or vicious starts (a vicious start is an output which gives totally erroneous pwm during the initial period following an update of the pwm registers). this feature is achieved by double buffering of the pwm d/a registers. 11.2 mux channel enable register (mcer) since the pwm output pins pwm0-pwm3 are multiplexed with the standard i/o port pins pa0-pa3 respectively, the mcer is provided to switch between the pwm and standard i/o function for each pin. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac3 r $002b w d9 d8 d7 d6 d5 d4 d3 d2 reset: 00000000 figure 11-8. d/a data register 3 (dac3) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac3 r $002c w d1 d0 reset: 00000000 figure 11-9. d/a data register 3 (dac3) (lsb) $000 $001 $200 $3ff 1023t 512t 512t 1023t 1024t t = 2 x t cyc
general release specification august 27, 1998 motorola pulse width modulator mc68HC05SB7 11-4 rev 2.1 each pwm channel is enabled by setting the corresponding dan-e bit in the mcer, shown in figure 11-11 . with a pwm output enabled, the corresponding port i/o is tri-stated automatically. reset clears the four dan-e bits. the outputs from four channels pwm system can be inhibited by setting the pwm_i bit in mcer. this bit can be used as a global pull logic ? for all the enabled das line before enter stop mode. the pwm_i bit is also used to disable the counter while the pwm is not in use for power saving. reset clears this bit. dan-e ?d/a channel n enable 1 = pwm output selected for pwmn/pan pin. 0 = standard i/o selected for pwmn/pan pin. pwm_i ?pwm inhibit 1 = inhibit all four pwm channels; pwm 10-bit counter also stopped. 0 = pwm channels not inhibited. 11.3 pwm during wait mode in wait mode, the oscillator is running even though the mcu clock is not present, the pwm outputs are not affected. to reduce power consumption in wait mode, it is recommended to disable the pwm. 11.4 pwm during stop mode in stop mode, the oscillator is stopped asynchronously with pwm operation. as a consequence, the pwm output will remain at the state at the moment when the oscillator is stopped. the pwm pins output depended on the state of pwm_i bit. if this bit is clear, it might be at its high or low state at that moment, and it remains at that state until stop mode is exited. if the pwm_i bit is set, it will be inhibited the state of pwm output in the process and pin output will be in logic low state. after stop mode is exited, the pwm output resumes its un?ished portion of the stopped cycle if pwm_i bit is clear by software. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcer r pwm_i 000 da3-e da2-e da1-e da0-e $002d w reset: 00000000 figure 11-11. mux channel enable register (mcer)
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-1 section 12 sm-bus 12.1 sm-bus introduction the system management bus (sm-bus) is a two wire, bidirectional serial bus which provides a simple, ef?ient way for data exchange between devices. this bus is suitable for applications which need frequent communications over a short distance between a number of devices. it also provides a ?xibility that allows additional devices to be connected to the bus. the maximum data rate is 100kbit/s, and the maximum communication distance and number of devices that can be connected is limited by a maximum bus capacitance of 400pf. the sm-bus is a true multi-master bus, including collision detection and arbitra- tion to prevent data corruption if two or more masters intend to control the bus simultaneously. this feature provides the capability for complex applications with multi-processor control. it may also be used for rapid testing and alignment of end products via external connections to an assembly-line computer. figure 12-1 shows a block diagram of the sm-bus interface. 12.2 sm-bus interface features fully compatible to sm-bus standard multi-master operation software programmable for one of 32 different serial clock frequencies software selectable acknowledge bit interrupt driven byte by byte data transfer arbitration lost driven interrupt with automatic mode switching from master to slave calling address identi?ation interrupt generate/detect the start or stop signal repeated start signal generation generate/recognize the acknowledge bit bus busy detection
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-2 rev 2.1 figure 12-1. sm-bus interface block diagram 12.3 sm-bus system configuration the sm-bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs and the logical ?nd function is performed on both lines by two pull up resistors. 12.4 sm-bus protocol normally a standard communication is composed of four parts, start signal, slave address transmission, data transfer, and stop signal. these are described brie? in the following sections and illustrated in figure 12-2 . internal bus frequency divider register address comparator address register 8 smen smien smsta smtx txak smcf smaas smbb smal srw smif srxak tx shift register rx shift register rx control tx control m-bus interrupt scl control sda control m-bus clock generator sync logic start, stop detector and arbitration start, stop generator and timing sync scl sda control register status register interrupt
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-3 figure 12-2. sm-bus transmission signal diagram 12.4.1 start signal when the bus is free, (i.e. no master device is engaging the bus and both scl and sda lines are at logical high) a master may initiate communication by sending a start signal. as shown in figure 12-2 , a start signal is de?ed as a high to low transition of sda while scl is high. this signal denotes the beginning of new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 12.4.2 slave address transmission the ?st byte of data transfer immediately after the start signal is the slave address transmitted by the master. this is a seven bit long calling address fol- lowed by a r/w-bit. the r/w-bit tells the slave the desired direction of data trans- fer. only the slave with a matched address will respond by sending back an acknowl- edge bit by pulling sda low on the 9th clock cycle. (see figure 12-2 ) 12.4.3 data transfer once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction speci?d by the r/w- bit sent by the calling master. 10 1 00011 1 0 1 00011 10 1 00011 1 0 1 00011 scl sda scl sda msb lsb msb lsb msb lsb msb lsb acknowledge bit no acknowledge start signal stop signal repeated start signal start signal stop signal acknowledge bit no acknowledge
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-4 rev 2.1 each data byte is 8 bits long. data can be changed only when scl is low and must be held stable when scl high as shown in figure 12-2 . the msb is trans- mitted ?st and each byte has to be followed by an acknowledge bit. this is sig- nalled by the receiving device by pulling the sda low on the 9th clock cycle. therefore one complete data byte transfer needs 9 clock cycles. if the slave receiver does not acknowledge the master, the sda line should be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new transfer. if the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it means an ?nd of data to the slave. the slave should now release the sda line for the master to generate a ?top or ?tart signal. 12.4.4 repeated start signal as shown in figure 12-2 , a repeated start signal is used to generate a start signal without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 12.4.5 stop signal with reference to figure 12-2 , the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without ?st generating a stop sig- nal. this is called repeat start. a stop signal is de?ed as a low to high transition of sda while scl is at logical high. 12.4.6 arbitration procedure this interface circuit is a true multi-master system which allows more than one master to be connected to it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. a data arbitration procedure determines the pri- ority. the masters will lose arbitration if they transmit logic ? while another trans- mits logic ?? the losing masters will immediately switch over to slave receive mode and stop its data and clock outputs. the transition from master to slave mode will not generate a stop condition in this case. meanwhile a software bit will be set by hardware to indicate loss of arbitration.
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-5 12.4.7 clock synchronization figure 12-3. clock synchronization since wired-and logic is performed on scl line, a high to low transition on the scl line will affect the devices connected to the bus. the devices start counting their low period and once a device's clock has gone low, it will hold the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore the synchronized clock scl will be held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 12-2 ). when all devices concerned have counted off their low period, the synchronized scl line will be released and go high. there will then be no difference between the device clocks and the state of the scl line and all devices will start counting their high periods. the ?st device to complete its high period will again pull the scl line low. 12.4.8 handshaking the clock synchronization mechanism can be used as a handshake in data trans- fer. slave devices may hold the scl low after completion of one byte. in such cases the device will halt the bus clock and force the master clock into a wait state until the slave releases the scl line. 12.5 sm-bus registers there are ?e registers used in the sm-bus interface. they are described in the following paragraphs. scl1 scl2 scl internal counter reset wait start counting high period
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-6 rev 2.1 12.5.1 sm-bus address register (smadr) smad1-smad7 are the slave address bits of the sm-bus module. 12.5.2 sm-bus frequency divider register (smfdr) fd0-fd4 are used for clock rate selection. the serial bit clock frequency is equal to the cpu clock divided by the divider shown in table 12-1 . for a 4mhz external crystal operation (2mhz internal operating frequency), the serial bit clock frequency of the sm-bus ranges from 460hz to 90909hz. after por the clock rate is set to 90909hz. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smadr r smad7 smad6 smad5 smad4 smad3 smad2 smad1 $0020 w reset: 0000000u bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smfdr r fd4 fd3 fd2 fd1 fd0 $0021 w reset: u u u 00000 table 12-1. sm-bus clock prescaler fd4, fd3, fd2, fd1, fd0 divider fd4,fd3, fd2, fd1, fd0 divider 00000 22 10000 352 00001 24 10001 384 00010 28 10010 448 00011 34 10011 544 00100 44 10100 704 00101 48 10101 768 00110 56 10110 896 00111 68 10111 1088 01000 88 11000 1408 01001 96 11001 1536 01010 112 11010 1792 01011 136 11011 2176 01100 176 11100 2816 01101 192 11101 3072 01110 224 11110 3584 01111 272 11111 4352
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-7 12.5.3 sm-bus control register (smcr) smen ?sm-bus enable if the sm-bus enable bit (smen) is set, the sm-bus interface system is enabled. if smen is cleared, the interface is reset and disabled. the smen bit must be set ?st before any bits of smcr are set. 1 = sm-bus enabled. 0 = sm-bus disabled. smien ?sm-bus interrupt enable if the sm-bus interrupt enable bit (smien) is set, the interrupt occurs provided the smif ?g in the status register is set and the i-bit in the condition code register is cleared. if smien is cleared, the sm-bus interrupt is disabled. 1 = sm-bus interrupt enabled. 0 = sm-bus interrupt disabled. smsta ?master/slave select upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operating mode changes from master to slave. in master mode, a bit clear immediately followed by a bit set of this bit gener- ates a repeated start signal (see figure 12-2 ) without generating a stop signal. 1 = sm-bus is set for master mode operation. 0 = sm-bus is set for slave mode operation. smtx ?transmit/receive mode select this bit selects the sm-bus to transmit or receive. 1 = sm-bus is set for transmit mode. 0 = sm-bus is set for receive mode. txak ?acknowledge enable if the transmit acknowledge enable bit (txak) is cleared, an acknowledge sig- nal will be sent out to the bus at the 9th clock bit after receiving one byte data. when txak is set, no acknowledge signal response (i.e., acknowledge bit = 1). 1 = do not send acknowledge signal. 0 = send acknowledge signal at 9th clock bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smcr r smen smien smsta smtx txak smux $0022 w reset: 000000uu
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-8 rev 2.1 smux ?sm-bus channel select the smux bit selects the channel for sm-bus communications. 1 = channel 1 (sda1 and scl1 pins) selected for sm-bus. 0 = channel 0 (sda0 and scl0 pins) selected for sm-bus. 12.5.4 sm-bus status register (smsr) smcf sm-bus data transfer complete this bit indicates when a byte of data is being transmitted. when this bit is set, the smif is also set. an interrupt request to the cpu is generated if the smien bit is also set. 1 = a byte transfer has been completed. 0 = a byte is being transferred. smaas ?sm-bus addressed as slave this bit is set when its own speci? address (smadr) matches the calling address. when this bit is set, the smif is also set. an interrupt request to the cpu is generated if the smien bit is also set. then cpu needs to check the srw bit and set its smtx bit accordingly. writing to the sm-bus control regis- ter clears this bit. 1 = currently addressed as a slave. 0 = not addressed. smbb ?sm-bus busy this bit indicates the status of the bus. when a start signal is detected, the smbb is set. if a stop signal is detected, it is cleared. 1 = sm-bus busy. 0 = sm-bus idle. smal ?sm-bus arbitration lost this bit is set by hardware when the arbitration procedure is lost during a mas- ter transmission. when this bit is set, the smif is also set. an interrupt request to the cpu is generated if the smien bit is also set. this bit must be cleared by software. 1 = lost arbitration in master mode. 0 = no arbitration lost. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smsr r smcf smaas smbb smal srw smif rxak $0023 w smal clr smif clr reset: 10000001
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-9 srw ?slave read/write select when smaas is set, the r/w command bit of the calling address sent from master is latched into the r/w command bit (srw). by checking this bit, the cpu can select slave transmit/receive mode according to the command of master. 1 = read from slave, from calling master. 0 = write to slave from calling master. smif ?sm-bus interrupt flag 1 = an sm-bus interrupt has occurred. 0 = an sm-bus interrupt has not occurred. this bit is set when one of the following events occur: transmission (either transmit or receive mode) of one byte completed. the bit is set at the falling edge of the 9th clock. receive a calling address which matches its own speci? address in slave receive mode. arbitration lost. rxak ?receive acknowledge when this bit is ?? it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is ?? it means no acknowledge signal is detected at the 9th clock. this bit is set upon reset. 1 = no acknowledgment signal detected. 0 = acknowledgment signal detected after 8 bits data transmitted.
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-10 rev 2.1 12.5.5 sm-bus data i/o register (smdr) in master transmit mode, data written to this register is sent (msb ?st) to the bus automatically. in master receive mode, reading from this register initiates receiving of the next byte of data. in slave mode, the same function is available after it is addressed. 12.5.6 sm-bus logic level two choices of logic level is available for the sm-bus: ttl or cmos. sminlev ?sm-bus input level select this read/write bit selects whether sm-bus input level is ttl or cmos. reset clears the sminlev bit. 1 = ttl input level is selected. 0 = cmos input level is selected. 12.5.7 scl as16-bit timer input capture the scl signal can be routed to the 16-bit timer input capture by setting the tcsel bit in the miscellaneous control register. tcsel ?16-bit timer input capture source select this read/write bit selects the input capture source to the 16-bit timer. reset clears tcsel. 1 = sm-bus scl is routed to input capture of 16-bit timer. 0 = cpf or external tcap pin (depends on the state of icen bit in acr, $1d) is routed to 16-bit timer. see section input capture of 16-bit timer for more details. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smdr r smd7 smd6 smd5 smd4 smd3 smd2 smd1 smd0 $0024 w reset: 00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 figure 12-4. miscellaneous control register (mcr)
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-11 12.6 programming considerations 12.6.1 initialization 1. update frequency divider register (fdr) to select a scl frequency. 2. update sm-bus address register (smadr) to de?e its own slave address. 3. set smen bit of sm-bus control register (smcr) to enable the sm- bus interface system. 4. modify the bits of sm-bus control register (smcr) to select master/ slave mode, transmit/receive mode, interrupt enable or not. 12.6.2 generation of a start signal and the first byte of data transfer after completion of the initialization procedure, serial data can be transmitted by selecting the ?aster transmitter mode. if the device is connected to a multi-mas- ter bus system, the state of the sm-bus busy bit (smbb) must be tested to check whether the serial bus is free. if the bus is free (smbb = 0), the start condition and the ?st byte (the slave address) can be sent. an example of a program which generates the start signal and transmits the ?st byte of data (slave address) is shown below: sei ; disable interrupt chfalg brset 5,smsr,chflag ; check the smbb bit of the ; status register. if it is ; set, wait until it is clear txstart bset 4,smcr ; set transmit mode bset 5,smcr ; set master mode ; i.e. generate start condition lda #calling ; get the calling address sta smdr ; transmit the calling ; address cli ; enable interrupt 12.6.3 software responses after transmission or reception of a byte transmission or reception of a byte will set the data transferring bit (smcf) to 1, which indicates one byte communication is ?ished. also, the sm-bus interrupt bit (smif) is set to generate an sm-bus interrupt if the interrupt function is enable during initialization. software must clear the smif bit in the interrupt routine ?st. the smcf bit will be cleared by reading from the sm-bus data i/o register (smdr) in receive mode or writing to smdr in transmit mode. software may serve the sm-bus i/o in the main program by monitoring the smif bit if the inter- rupt function is disabled. the following is an example of a software response by a ?aster transmitter in the interrupt routine (see figure 12-5 ).
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-12 rev 2.1 figure 12-5. flow-chart of sm-bus interrupt routine clear smif master mode tx/rx last byte to be read last byte transmitted tx rx rxak=0 n write next byte to smdr generate stop signal y n y set txak = 1 n n generate stop signal y read data from smdr and store clear smal y n smaas = 1 smaas = 1 srw= 1 y tx/rx read smdr and store set tx mode write to smdr set rx mode dummy read from smdr ack from receiver tx next byte switch to rx mode dummy read from smdr arbitration lost last 2nd byte to be read rti n y tx rx n y n n (write) y (read) yn
august 27, 1998 general release specification mc68HC05SB7 sm-bus motorola rev 2.1 12-13 isr bclr 1,smsr ; clear the smif flag brclr 5,smcr,slave ; check the smsta flag, ; branch if slave mode brclr 4,smcr,receive ; check the mode flag, ; branch if in receive mode brset 0,smsr,end ; check ack from receiver ; if no ack, end of ; transmission transmit lda databuf ; get the next byte of data sta smdr ; transmit the data 12.6.4 generation of the stop signal a data transfer ends with a stop signal generated by the ?aster device. a mas- ter transmitter can simply generate a stop signal after all the data has been transmitted. the following is an example showing how a stop condition is gener- ated by a master transmitter: mastx brset 0,smsr,end ; if no ack, branch to end lda txcnt ; get value from the ; transmitting counter beq end ; if no more data, branch to ; end lda databuf ; get next byte of data sta smdr ; transmit the data dec txcnt ; decrease the txcnt bra emastx ; exit end bclr 5,smcr ; generate a stop condition emastx rti ; return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. this can be done by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated ?st. the following is an example showing how a stop signal is generated by a master receiver. masr dec rxcnt beq enmasr ; last byte to be read lda rxcnt deca ; check last 2nd byte to ; be read bne nxmar ; not last one or last second lamar bset 3,smcr ; last second, disable ack ; transmitting bra nxmar enmasr bclr 5,smcr ; last one, generate ?top ; signal nxmar lda smdr ; read data and store sta rxbuf rti
general release specification august 27, 1998 motorola sm-bus mc68HC05SB7 12-14 rev 2.1 12.6.5 generation of a repeated start signal if at the end of data transfer the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without ?st generating a stop signal. a program example is shown below. restart bclr 5,smcr ; another start (restart) is bset 5,smcr ; generated by these two ; consequence instruction lda #calling ; get the calling address sta smdr ; transmit the calling address 12.6.6 slave mode in the slave service routine, the master addressed as slave bit (smaas) should be tested to see if a calling of its own address has just been received. if smaas is set, software should set the transmit/receive mode select bit (smtx bit of smcr) according to the r/w-command bit (srw). writing to the smcr clears the smaas automatically. a data transfer may then be initiated by writing information to smdr or dummy reading from smdr. in the slave transmitter routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. if rxak is set, indicating an ?nd of data signal from the master receiver, then it must switch from transmitter mode to receiver mode by software and a dummy read must follow to release the scl line so that the master can generate a stop signal. 12.6.7 arbitration lost if more than one master want to acquire the bus simultaneously, only one master wins and the others lost arbitration. the arbitration lost devices immediately switch to slave receive mode by hardware. their data output to the sda line is stopped, but internal transmitting clock still run until the end of the byte transmitting. an interrupt occurs when this dummy ?yte transmitting is accomplished with smal=1 and smsta = 0. if one master attempt to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmis- sion; switch the smsta bit from 1 to 0 without generating stop condition; gener- ate an interrupt to cpu and set the smal to indicate that the attempt to engage the bus is failed. consideration of these cases, the slave service routine should test the smal ?st, software should clear the smal bit if it is set. 12.7 operation during wait mode during wait mode the sm-bus block is idle. if in slave mode it will wake up on receiving a valid start condition. if the interrupt is enabled the cpu will come out of wait mode after the end of a byte transmission. 12.8 operation during stop mode in stop mode the sm-bus is disabled.
august 27, 1998 general release specification mc68HC05SB7 current sense amplifier motorola rev 2.1 13-1 section 13 current sense amplifier the current sense ampli?r module, used in conjunction with the analog sub- system, is designed to monitor charge and discharge currents in smart battery applications. 13.1 current sense amplifier application a typical connection for the current sense ampli?r (csa) block is illustrated in figure 13-1 . with a sense resistor, r sense of 0.01 w , the voltage setup across the node csa and v ss (ground) will vary to the current (in either charging or discharg- ing mode) as shown in table 13-1 . in this case, the csa is required to measure a current from 10ma to 5a over the operating temperature from 0 c to 70 c. with the a/d in the analog subsystem set up for 12-bit resolution, the step size is approximately 1.22mv (v dd =5v). to measure the 0.1mv for the 10ma current ?w, a gain of greater than 10 is required. the csa module is designed with two gain settings, 10 and 30. with a 10-bit a/d, and a gain of 30, the csa can measure current with a typical resolution of 17ma steps. after ampli?ation, the resultant signal is fed to channel 6 (mux6) of the analog subsystem for a/d conversion. table 13-1. voltage across the sense resistor against current current flowing voltage across the sense resistor, r sense 10ma 0.1mv 1a 10mv 5a 50mv r sense =0.01 w
general release specification august 27, 1998 motorola current sense amplifier mc68HC05SB7 13-2 rev 2.1 figure 13-1. current sense ampli?r block 13.2 current sense interrupt the csa can generate an interrupt once it detects a (discharge) current passes through the current sensing resistor, r sense . the trip current depends on the value of the sense resistor; it is voltage developed across r sense , v det that trips the interrupt. v det is set typically at 15mv, with 10mv being the minimum. 13.3 csa status and control register (csscr) the csa status and control register is shown in figure 13-2 . port b 0.01 w batt+ batt i/o logic csen d q gain adjustment cden v ss + pb2/ pb3/ cs0 cs1 v mid (for internal test) cscal (bit 7 of $0a) (bit 4 of $0a) x10 (bit 5 of $0a) x30 (bit 6 of $0a) to analog mux 6 input csa + v dd (bit 3 of $0a) cdet interrupt r cdie cdifr (bit 2 of $0a) cden (bit 3 of $0a) cssel (bit 3 of $0b) logic (bit 1 of $0a) r sense v det typically 15mv cs0 and cs1 pins are not available for csa functions when osc1 and osc2 are used; i.e. external crystal osc. option is used.
august 27, 1998 general release specification mc68HC05SB7 current sense amplifier motorola rev 2.1 13-3 csen ?current sense ampli?r enable this read/write bit enables the csa module. reset clears the csen bit. 1 = csa block enabled. 0 = csa block disabled. x30, x10 ?current sense ampli?r gain select these read/write bits enable the respective gain to be selected. see table 13-2 . reset clears the x30 and x10 bits. table 13-2. current sense ampli?r gain select cscal ?current sense ampli?r calibration enable this read/write bit enables the csa calibration. reset clears the cscal bit. 1 = csa calibration enabled; current ampli?r input connected to ground (v ss ). 0 = csa calibration disabled; current ampli?r input from csa pin. cden ?current detect enable this read/write bit enables the current detect comparator and current detect output pin (cs0 or cs1) logic. reset clears the cden bit. 1 = current detect comparator enabled. 0 = current detect comparator disabled. cdie ?current detect interrupt enable this read/write bit enables interrupts caused by detecting the current passing through the sensing resistor, r sense . reset clears the cdie bit. 1 = current detect interrupt enabled. 0 = current detect interrupt disabled. cdifr ?current detect interrupt flag reset writing a logic ? to this write-only bit clears the cdif bit. cdifr always reads as a logic zero. reset does not affect cdifr. 1 = clear cdif bit. 0 = no affect on cdif bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csscr r csen x30 x10 cscal cden cdie 0 cdif $000a w cdifr reset: 00000000 figure 13-2. csa status and control register (csscr) x30 x10 gain selected 0 don? care x10 1 0 x30 1 1 undetermined
general release specification august 27, 1998 motorola current sense amplifier mc68HC05SB7 13-4 rev 2.1 cdif ?current detect interrupt flag this read-only bit is set when the voltage developed across the sense resistor, r sense is equal to or greater than v det (the csa comparator trip voltage, typically ?5mv) cdif generates an interrupt request to the cpu if cdie is also set. the cdif bit is cleared by writing a logic ? to the cdifr bit. writing to cdif has no effect. reset clears cdif. 1 = current detect interrupt has occurred. 0 = no current detect interrupt since cdif last cleared. if the osc1 and osc2 pins are not enabled (by mask option). the current detect interrupt from cdif bit can be re?cted to one of two output port pins, pb2/cs0 and pb3/cs1. cssel ?current sense detect output select this read/write bit selects either cs0 pin or cs1 pin is used to re?ct the cur- rent detect interrupt. reset clears the cssel bit. 1 = cs1 enabled, cs0 disabled. 0 = cs0 enabled, cs1 disabled. table 13-3. current detect output select cs0 and cs1 are not available when osc1 and osc2 are used for external oscil- lator option. 13.4 csa operation during wait mode in wait mode the csa module continues to operate and may generate an inter- rupt to trigger the mcu out of wait mode. 13.5 csa operation during stop mode in stop mode the csa module is disabled; but a csa interrupt (by cdif) can wake-up the mcu from the stop mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 u = unaffected by reset figure 13-3. miscellaneous control register (mcr) cden cssel pb2/cs0 pb3/cs1 0 0 pb2 pb3 0 1 pb2 pb3 1 0 cs0 pb3 1 1 pb2 cs1
august 27, 1998 general release specification mc68HC05SB7 temperature sensor motorola rev 2.1 14-1 section 14 temperature sensor the mc68HC05SB7 mcu can measure temperature in two ways: by using the internal temperature sensor, or by using an external thermistor. 14.1 internal temperature sensor the internal temperature sensor is designed to measure temperature over the 0 c to 70 c range; with its voltage output connected to channel 5 of the analog subsystem (an5, see analog subsystem section). the temperature sensor is disabled/enabled by the tsen bit in the miscellaneous control register at $0b. the tsen bit also disables/enables the bandgap reference voltage. tsen ?internal temperature sensor and bandgap reference enable this read/write bit enables the internal temperature sensor and bandgap refer- ence. reset clears tsen. 1 = temperature sensor and bandgap reference enabled. 0 = temperature sensor and bandgap reference disabled. note the temperature gradient is typically 2.2mv/ c ?0%. the internal temperature sensor is a semiconductor type sensor. due to process variations, the absolute output voltage at a given temperature will vary from one device to another. it is the users responsibility to measure and calibrate the temperature sensor output voltage when the mcu is in the target system. as an option, the temperature sensor voltage at 80 c is available preprogrammed into the peprom. see peprom section. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr r tsen lvron 0 sclk cssel tcsel esven sminlev $000b w copon reset: 01000000 figure 14-1. miscellaneous control register (mcr)
general release specification august 27, 1998 motorola temperature sensor mc68HC05SB7 14-2 rev 2.1 14.2 external temperature sensor in fast charge control applications, where close monitoring of the charging pro- cess is required (especially temperature), an external temperature sensor (ther- mistor) is recommended. this external thermistor connects to the tm pin (see figure 14-2 ), and its voltage measured via channel 4 (an4, see analog sub- system section) of the analog subsystem. for faster temperature response time and more accurate measurement (required for fast charge control), the thermistor should be mounted directly to the battery pack. figure 14-2. external temperature sensor connection 14.3 temperature sensor operation during wait mode during wait mode the temperature sensor continues to operate normally. 14.4 temperature sensor operation during stop mode in stop mode the temperature sensor is disabled. batt+ batt v dd tm vm mc68HC05SB7 thermistor
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-1 section 15 analog subsystem the analog subsystem of the mc68HC05SB7 is based on an on-chip voltage comparator as shown in figure 15-1 . this con?uration provides following features: the voltage comparator with external access to both inverting and non- inverting inputs the voltage comparator can be connected as a single-slope a/d. the possible single-slope a/d connection provides the following features: a/d conversions can use v dd or an external voltage as a reference with software used to calculate ratiometric or absolute results channel access to up to eight inputs via multiplexer control with independent multiplexer control allowing multiple input connections access to v dd and v ss for calibration divide by 2 to extend input voltage range the comparator can be inverted to calculate input offsets internal sample and hold capacitor voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the unknown input voltage that is being measured. the beginning of the a/d conversion time can be started by several means: output compare from the 16-bit programmable timer timer over?w from the 16-bit programmable timer direct software control via a register bit the end of the a/d conversion time can be captured by several means: input capture in the 16-bit programmable timer interrupt generated by the comparator output software polling of the comparator output using software loop time
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-2 rev 2.1 figure 15-1. analog subsystem block diagram analog interrupt cap v dd tof ocf charge current chg + pb4 an3 inv comp mux2 mux0 mux1 sample i chg hold inv dhold vref mux3 mux2 mux1 mux0 i dischg 2 to 1 mux 16-bit prog. analog tcap internal hc05 bus cmp cap 100k 100k mux3 mux2 mux1 channel select bus mux0 vref isen cpen analog control register (acr) icen cpie mux register 1 (amux1) analog status register (asr) cpf timer atd2 atd1 icf control logic pb1 tcap mux7 mux6 mux5 mux4 analog mux register 2 (amux2) tm mux7 mux4 ibref mux3 mux6 mux7 mux6 mux5 mux4 an4 mux5 ibref ibref v ss v aoff denotes internal chip av ss 2 to 1 mux scl tcsel v dd vm an7 pb5 an2 pb6 an1 pb7 an0 portb logic portb logic portb logic portb logic internal reference bandgap csa internal sensor temperature tsen bit 7 of mcr ($0b) bit 2 of mcr ($0b) + an5 an6 current sense amplifier circuit v ib (see figure 13-1)
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-3 15.1 analog multiplex registers the analog multiplex registers (amux1 and amux2) control the general inter- connection and operation. the control bits in amux1 and amux2 are shown in figure 15-2 and figure 15-2 respectively. hold, dhold these read/write bits control the source connection to the input to the negative input of voltage comparator shown in figure 15-1 . this allows the channel selection bus or the 1:2 divided channel selection bus to charge the internal sample capacitor and to also be presented to comparator. the decoding of these sources is given in table 15-1 . during a reset the hold bit is set and the dhold bit is cleared, which connects the internal sample capacitor to the channel selection bus. and since a reset also clears the mux0:7 bits then the channel selection bus will be connected to v ss and the internal sample capaci- tor will be discharged to v ss following the reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 amux1 r hold dhold inv vref mux3 mux2 mux1 mux0 $0003 w reset: 10000000 figure 15-2. analog multiplex register 1 (amux1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 amux2 r 0 0 ibref mux7 mux6 mux5 mux4 $0007 w reset: 00000000 figure 15-3. analog multiplex register 2 (amux2) table 15-1. comparator input sources hold dhold case source to negative input of comparator 0 0 sample hold internal sample capacitor connected to only the neg- ative input of comparator; and subjected to a very low leakage current. 0 1 divided input signal to channel selection bus is divided by 2 and connected to both the internal sample capacitor and negative input of comparator. 10 direct input signal to channel selection bus is connected directly to both the internal sample capacitor and negative input of comparator. 1 1 not allowed
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-4 rev 2.1 note when sampling a voltage for later conversion the hold and dhold bit should be cleared before making any changes in the mux channel selection. if the mux channel and the hold/dhold are changed on the same write cycle to the amux1 register, the sampled voltage may be altered during the channel switching. inv this is a read/write bit that controls the phase of the voltage comparator. this bit allows voltage comparisons with either input node of the voltage comparator to be presented to the rest of the circuit as the ?ositive or ?egative input. the voltage comparator is de?ed as non-inverted when the internal positive node is connected to the external positive input and the output is not inverted. in this case the output will go to a logical one when the voltage on the positive input is higher than the voltage on the negative input. any input offset voltage in the voltage comparator will be with respect to the negative input. the voltage comparator is de?ed as inverted when the internal negative node is connected to the external positive input and the output is inverted. in this case the output will still go to a logical one when the voltage on the positive input is higher than the voltage on the negative input. in the inverted case any input offset voltage in the voltage comparator will be with respect to the positive input. this bit is cleared by a reset of the device. 1 = the voltage comparator is internally inverted. 0 = the voltage comparator is not internally inverted. figure 15-4. inv bit action note the effect of changing the state of the inv bit is to only change the polarity of the input offset voltage. it does not change the output phase of the cpf ?g with respect to the external port pins. the comparator may generate an output ?g when the inputs are exchanged due to a change in the state of the inv bit. it is therefore recommended that the inv bit + comp v io v+ v inv=0 rise when v+ > v + comp v io v+ v inv=1 rise when v+ > v
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-5 not be changed while waiting for a comparator ?g. further, any changes to the state of the inv bit should be followed by writing a logical one to cpfr bit to clear an extraneous cpf ?g that may have occurred. vref this is a read/write bit that connects the channel select bus to v dd for purposes of making a reference voltage measurement. it cannot be selected if any of the other input sources to the channel select bus are selected as shown in table 15-2 . this bit is cleared by a reset of the device. 1 = channel select bus connected to v dd if mux7:0 and ibref are cleared. 0 = channel select bus cannot be connected to v dd . ibref this is a read/write bit that connects the channel select bus to v ib for purposes of making a reference voltage measurement. it cannot be selected if any of the other input sources to the channel select bus are selected as shown in table 15-2 . this bit is cleared by a reset of the device. 1 = channel select bus connected to v ib if mux7:0 and vref are cleared. 0 = channel select bus cannot be connected to v ib . mux7:0 these are read/write bits that connect the analog subsystem pins to the chan- nel select bus and voltage comparator for purposes of making a voltage mea- surement. they can be selected individually or combined with any of the other input sources to the channel select bus as shown in table 15-2 . note the v aoff voltage source shown in figure 15-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single v ss pin. the offset raises the internal v ss reference (av ss ) in the analog subsystem with respect to the external v ss pin. turning on the v ss mux to the channel select bus connects it to this internal avss reference line. when making a/d conversions this av ss offset gets placed on the external ramping capacitor since the discharge device on the cap pin discharges the external capacitor to the internal av ss line. under these circumstances the positive input (+) to the comparator will always be higher than the negative input ( ) until the negative input reaches the av ss offset voltage plus any offset in the comparator. therefore, input voltages cannot be resolved if they are less than the sum of the av ss offset and the comparator offset, because they will always yield a low output from the comparator
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-6 rev 2.1 table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss 0000000000 zzzzzzzzzzon xx00000001 zzzzzzzzzonz xx00000010 zzzzzzzzonzz xx00000011 zzzzzzzzononz xx00000100 zzzzzzzonzzz xx00000101 zzzzzzzonzonz xx00000110 zzzzzzzononzz xx00000111 zzzzzzzonononz xx00001000 zzzzzzonzzzz xx00001001 zzzzzzonzzonz xx00001010 zzzzzzonzonzz xx00001011 zzzzzzonzononz xx00001100 zzzzzzononzzz xx00001101 zzzzzzononzonz xx00001110 zzzzzzonononzz xx00001111 zzzzzzononononz xx00010000 zzzzzonzzzzz xx00010001 zzzzzonzzzonz xx00010010 zzzzzonzzonzz xx00010011 zzzzzonzzononz xx00010100 zzzzzonzonzzz xx00010101 zzzzzonzonzonz xx00010110 zzzzzonzononzz xx00010111 zzzzzonzonononz xx00011000 zzzzzononzzzz xx00011001 zzzzzononzzonz xx00011010 zzzzzononzonzz xx00011011 zzzzzononzononz xx00011100 zzzzzonononzzz xx00011101 zzzzzonononzonz
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-7 xx00011110 zzzzzononononzz xx00011111 zzzzzonononononz xx00100000 zzzzonzzzzzz xx00100001 zzzzonzzzzonz xx00100010 zzzzonzzzonzz xx00100011 zzzzonzzzononz xx00100100 zzzzonzzonzzz xx00100101 zzzzonzzonzonz xx00100110 zzzzonzzononzz xx00100111 zzzzonzzonononz xx00101000 zzzzonzonzzzz xx00101001 zzzzonzonzzonz xx00101010 zzzzonzonzonzz xx00101011 zzzzonzonzononz xx00101100 zzzzonzononzzz xx00101101 zzzzonzononzonz xx00101110 zzzzonzonononzz xx00101111 zzzzonzononononz xx00110000 zzzzononzzzzz xx00110001 zzzzononzzzonz xx00110010 zzzzononzzonzz xx00110011 zzzzononzzononz xx00110100 zzzzononzonzzz xx00110101 zzzzononzonzonz xx00110110 zzzzononzononzz xx00110111 zzzzononzonononz xx00111000 zzzzonononzzzz xx00111001 zzzzonononzzonz xx00111010 zzzzonononzonzz xx00111011 zzzzonononzononz xx00111100 zzzzononononzzz table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-8 rev 2.1 xx00111101 zzzzononononzonz xx00111110 zzzzonononononzz xx00111111 zzzzononononononz xx0 ! 000000 z z z on zzzzzzz xx01000001 z z z on zzzzzonz xx01000010 z z z on zzzzonzz xx01000011 z z z on zzzzononz xx01000100 z z z on z z z on z z z xx01000101 z z z on z z z on z on z xx01000110 z z z on z z z on on z z xx01000111 z z z on z z z on on on z xx01001000 z z z on z z on zzzz xx01001001 z z z on z z on z z on z xx01001010 z z z on z z on z on z z xx01001011 z z z on z z on z on on z xx01001100 z z z on z z on on z z z xx01001101 z z z on z z on on z on z xx01001110 z z z on z z on on on z z xx01001111 z z z on z z on on on on z xx01010000 z z z on z on zzzzz xx01010001 z z z on z on z z z on z xx01010010 z z z on z on z z on z z xx01010011 z z z on z on z z on on z xx01010100 z z z on z on z on z z z xx01010101 z z z on z on z on z on z xx01010110 z z z on z on z on on z z xx01010111 z z z on z on z on on on z xx01011000 z z z on z on on zzzz xx01011001 z z z on z on on z z on z xx01011010 z z z on z on on z on z z xx01011011 z z z on z on on z on on z table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-9 xx01011100 z z z on z on on on z z z xx01011101 z z z on z on on on z on z xx01011110 z z z on z on on on on z z xx01011111 z z z on z on on on on on z xx01100000 z z z on on zzzzzz xx01100001 z z z on on zzzzonz xx01100010 z z z on on z z z on z z xx01100011 z z z on on z z z on on z xx01100100 z z z on on z z on z z z xx01100101 z z z on on z z on z on z xx01100110 z z z on on z z on on z z xx01100111 z z z on on z z on on on z xx01101000 z z z on on z on zzzz xx01101001 z z z on on z on z z on z xx01101010 z z z on on z on z on z z xx01101011 z z z on on z on z on on z xx01101100 z z z on on z on on z z z xx01101101 z z z on on z on on z on z xx01101110 z z z on on z on on on z z xx01101111 z z z on on z on on on on z xx01110000 z z z on on on zzzzz xx01110001 z z z on on on z z z on z xx01110010 z z z on on on z z on z z xx01110011 z z z on on on z z on on z xx01110100 z z z on on on z on z z z xx01110101 z z z on on on z on z on z xx01110110 z z z on on on z on on z z xx01110111 z z z on on on z on on on z xx01111000 z z z on on on on zzzz xx01111001 z z z on on on on z z on z xx01111010 z z z on on on on z on z z table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-10 rev 2.1 xx01111011 z z z on on on on z on on z xx01111100 z z z on on on on on z z z xx01111101 z z z on on on on on z on z xx01111110 z z z on on on on on on z z xx01111111 z z z on on on on on on on z xx10000000 z z on zzzzzzzz xx10000001 z z on zzzzzzonz xx10000010 z z on zzzzzonzz xx10000011 z z on zzzzzononz xx10000100 z z on zzzzonzzz xx10000101 z z on zzzzonzonz xx10000110 z z on zzzzononzz xx10000111 z z on zzzzonononz xx10001000 z z on z z z on zzzz xx10001001 z z on z z z on z z on z xx10001010 z z on z z z on z on z z xx10001011 z z on z z z on z on on z xx10001100 z z on z z z on on z z z xx10001101 z z on z z z on on z on z xx10001110 z z on z z z on on on z z xx10001111 z z on z z z on on on on z xx10010000 z z on z z on zzzzz xx10010001 z z on z z on z z z on z xx10010010 z z on z z on z z on z z xx10010011 z z on z z on z z on on z xx10010100 z z on z z on z on z z z xx10010101 z z on z z on z on z on z xx10010110 z z on z z on z on on z z xx10010111 z z on z z on z on on on z xx10011000 z z on z z on on zzzz xx10011001 z z on z z on on z z on z table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-11 xx10011010 z z on z z on on z on z z xx10011011 z z on z z on on z on on z xx10011100 z z on z z on on on z z z xx10011101 z z on z z on on on z on z xx10011110 z z on z z on on on on z z xx10011111 z z on z z on on on on on z xx10100000 z z on z on zzzzzz xx10100001 z z on z on zzzzonz xx10100010 z z on z on z z z on z z xx10100011 z z on z on z z z on on z xx10100100 z z on z on z z on z z z xx10100101 z z on z on z z on z on z xx10100110 z z on z on z z on on z z xx10100111 z z on z on z z on on on z xx10101000 z z on z on z on zzzz xx10101001 z z on z on z on z z on z xx10101010 z z on z on z on z on z z xx10101011 z z on z on z on z on on z xx10101100 z z on z on z on on z z z xx10101101 z z on z on z on on z on z xx10101110 z z on z on z on on on z z xx10101111 z z on z on z on on on on z xx10110000 z z on z on on zzzzz xx10110001 z z on z on on z z z on z xx10110010 z z on z on on z z on z z xx10110011 z z on z on on z z on on z xx10110100 z z on z on on z on z z z xx10110101 z z on z on on z on z on z xx10110110 z z on z on on z on on z z xx10110111 z z on z on on z on on on z xx10111000 z z on z on on on zzzz table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-12 rev 2.1 xx10111001 z z on z on on on z z on z xx10111010 z z on z on on on z on z z xx10111011 z z on z on on on z on on z xx10111100 z z on z on on on on z z z xx10111101 z z on z on on on on z on z xx10111110 z z on z on on on on on z z xx10111111 z z on z on on on on on on z xx1 ! 000000 z z on on zzzzzzz xx11000001 z z on on zzzzzonz xx11000010 z z on on zzzzonzz xx11000011 z z on on zzzzononz xx11000100 z z on on z z z on z z z xx11000101 z z on on z z z on z on z xx11000110 z z on on z z z on on z z xx11000111 z z on on z z z on on on z xx11001000 z z on on z z on zzzz xx11001001 z z on on z z on z z on z xx11001010 z z on on z z on z on z z xx11001011 z z on on z z on z on on z xx11001100 z z on on z z on on z z z xx11001101 z z on on z z on on z on z xx11001110 z z on on z z on on on z z xx11001111 z z on on z z on on on on z xx11010000 z z on on z on zzzzz xx11010001 z z on on z on z z z on z xx11010010 z z on on z on z z on z z xx11010011 z z on on z on z z on on z xx11010100 z z on on z on z on z z z xx11010101 z z on on z on z on z on z xx11010110 z z on on z on z on on z z xx11010111 z z on on z on z on on on z table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-13 xx11011000 z z on on z on on zzzz xx11011001 z z on on z on on z z on z xx11011010 z z on on z on on z on z z xx11011011 z z on on z on on z on on z xx11011100 z z on on z on on on z z z xx11011101 z z on on z on on on z on z xx11011110 z z on on z on on on on z z xx11011111 z z on on z on on on on on z xx11100000 z z on on on zzzzzz xx11100001 z z on on on zzzzonz xx11100010 z z on on on z z z on z z xx11100011 z z on on on z z z on on z xx11100100 z z on on on z z on z z z xx11100101 z z on on on z z on z on z xx11100110 z z on on on z z on on z z xx11100111 z z on on on z z on on on z xx11101000 z z on on on z on zzzz xx11101001 z z on on on z on z z on z xx11101010 z z on on on z on z on z z xx11101011 z z on on on z on z on on z xx11101100 z z on on on z on on z z z xx11101101 z z on on on z on on z on z xx11101110 z z on on on z on on on z z xx11101111 z z on on on z on on on on z xx11110000 z z on on on on zzzzz xx11110001 z z on on on on z z z on z xx11110010 z z on on on on z z on z z xx11110011 z z on on on on z z on on z xx11110100 z z on on on on z on z z z xx11110101 z z on on on on z on z on z xx11110110 z z on on on on z on on z z table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-14 rev 2.1 x = don? care z = high impedance 15.2 analog control register the analog control register (acr) controls the power up, interrupt and ?g oper- ation. the analog subsystem draws about 470 m a of current while it is operating. the resulting power consumption can be reduced by powering down the analog subsystem when not in use. this can be done by clearing two enable bits (isen and cpen) in the acr at $001d. since these bits are cleared following a reset, the voltage comparator and the charge current source will be powered down fol- lowing a reset of the device. the control bits in the acr are shown in figure 15-2 . all the bits in this register are cleared by a reset of the device. xx11110111 z z on on on on z on on on z xx11111000 z z on on on on on zzzz xx11111001 z z on on on on on z z on z xx11111010 z z on on on on on z on z z xx11111011 z z on on on on on z on on z xx11111100 z z on on on on on on z z z xx11111101 z z on on on on on on z on z xx11111110 z z on on on on on on on z z xx11111111 z z on on on on on on on on z 0100000000 z on zzzzzzzzz 1000000000 on zzzzzzzzzz bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acr r chg atd2 atd1 icen cpie cpen isen $001d w reset: 00000000 figure 15-5. analog control register (acr) table 15-2. channel select bus combinations analog multiplex registers (amux1 and amux2) channel select bus connected to: v r e f i b r e f m u x 7 m u x 6 m u x 5 m u x 4 m u x 3 m u x 2 m u x 1 m u x 0 v dd v ib an7 an6 an5 an4 an3 an2 an1 an0 v ss
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-15 chg the chg enable bit allows direct control of the charge current source and the discharge device; and also re?cts the state of the discharge device. this bit is cleared if the isen enable bit is also cleared. this bit is cleared by a reset of the device. 1 = the charge current source is sourcing current out of the cap pin. writing a logical one enables the charging current out of the cap pin, if the isen bit is also set. 0 = the discharge device is sinking current into the cap pin. writing a logical zero disables the charging current and enables the discharging current into the cap pin. atd1:2 the atd1:2 enable bits select one of the four operating modes used for making a/d conversions via the single-slope method.these four modes are given in table 15-3 . these bits have no effect if the isen enable bit is cleared. these bits are cleared by a reset of the device; and thereby returning the analog sub- system to the manual a/d conversion method. table 15-3. a/d conversion options a/d option mode charge control a/d options current flow to/from cap isen atd2 atd1 chg disabled current source and discharge disabled 0xxx current control disabled, no source or sink cur- rent. 0 manual charge and discharge 1000 begin sinking current when the chg bit is cleared; and continue to sink current until the chg bit is set. 1001 begin sourcing current when the chg bit is set; and continue to source current until the chg bit is cleared. 1 manual charge and automatic discharge 1010 begin sinking current when the chg bit is cleared; and continue to sink current until the chg bit is set. (the chg bit is cleared by writing a logical zero to it; or when the cpf flag bit is set.) 1011 begin sourcing current when the chg bit is set; and continue to source current until the chg bit is cleared. (the chg bit is cleared by writing a logi- cal zero to it; or when the cpf flag bit is set.) 2 automatic charge and discharge (tof-icf) synchronized to timer 1100 the chg bit remains cleared as long as current is being sunk. begin sourcing current when the next timer tof occurs. 1101 the chg bit remains set as long as current is being sourced. begin sinking current when the next timer icf occurs.
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-16 rev 2.1 icen this is a read/write bit that enables a voltage comparison to trigger the input capture register of the programmable timer when the cpf ?g bit is set. there- fore an a/d conversion could be started by receiving an ocf or tof from the programmable timer; and then terminated when the voltage on the external ramping capacitor reaches the level of the unknown voltage. the time of termi- nation will be stored in the 16-bit buffer located at $0014 and $0015. this bit is automatically set whenever mode 2 or 3 is selected by setting the atd2 control bit. this bit is cleared by a reset of the device. 1 = connects the cpf ?g bit to the timer input capture register. 0 = connects the pb1/tcap pin to the timer input capture register. note when the icen bit is set the input capture function of the programmable timer is not connected to the pb1/tcap pin but is driven by the cpf output ?g from the comparator. to return to capturing times from external events, the icen bit must ?st be cleared before the timed event occurs. note the tcsel bit in the miscellaneous control register (bit 2 in $0b) must be cleared for icen control. tcsel=1 will select the scl signal from the smbus as 16-bit timer input capture source, irrespective of icen setting. cpie this is a read/write bit that enables an analog interrupt when the cpf ?g bits is set to a logical one. this bit is cleared by a reset of the device. 1 = enables analog interrupt when comparator ?g bit is set. 0 = disables analog interrupt when comparator ?g bit is set. 3 automatic charge and discharge (ocf-icf) synchronized to timer 1110 the chg bit remains cleared as long as current is being sunk. begin sourcing current when the next timer ocf occurs. 1111 the chg bit remains set as long as current is being sourced. begin sinking current when the next timer icf occurs. table 15-3. a/d conversion options a/d option mode charge control a/d options current flow to/from cap isen atd2 atd1 chg
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-17 cpen the cpen enable bit will power down voltage comparator in the analog sub- system. powering down a comparator will drop the supply current by about 100 m a. this bit is cleared by a reset of the device. 1 = writing a logical one powers up voltage comparator. 0 = writing a logical zero powers down voltage comparator note the voltage comparator powers up slower than digital logic; and its output may go through indeterminate states which might set the cpf ?g. it is therefore recommended to power up the charge current source ?st (isen); then to power up the comparator, and ?ally clear the bit by writing a logic one to the cpfr bit in the acr. isen the isen enable bit will power down the charge current source and disable the discharge device in the analog subsystem. powering down the current source will drop the supply current by about 200 m a. this bit is cleared by a reset of the device. 1 = writing a logical one powers up the ramping current source and enables the discharge device on the cap pin. 0 = writing a logical zero powers down the ramping current source and disables the discharge device on the cap pin. note the analog subsystem has support circuitry which draws about 70 m a of current. this current will be powered down if the comparator and the charge current source are powered down (isen and cpen all cleared). powering up the comparator or the charge current source will activate the support circuitry. 15.3 analog status register the analog status register (asr) controls the interrupt and ?g operation. the control bits in the asr are shown in figure 15-2 . all the bits in this register are cleared by a reset of the device. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 asr r cpf 000000 $001e w cpfr reset: 00000000 figure 15-6. analog status register
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-18 rev 2.1 cpf this read-only ?g bit is set when the voltage on the positive input of compara- tor rises above the voltage on its negative input. this bit is reset by writing a logical one to the cpfr reset bit in the asr. this bit is cleared by a reset of the device. 1 = the voltage on positive input of comparator was above the voltage on its negative input since cpf had been cleared. 0 = the voltage on positive input of comparator has not been above the voltage on its negative input since cpf had been cleared. cpfr writing a logical one to this write-only ?g clears the cpf ?g in the asr. writ- ing a logical zero to this bit has no effect. reading the cpfr bit will return a logical zero. by default this bit looks cleared following a reset of the device. 1 = clears the cpf ?g bit. 0 = no effect. note the cpfr bit should be written with a logical one following a power up of the comparator. this will clear out any latched cpf ?g bit which might have been set during the slower power up sequence of the analog circuitry. if both inputs to the comparator are above the maximum common-mode input voltage (v dd 1.5v) the output of the comparator is indeterminate and may set the comparator ?g. applying a reset to the device may only temporarily clear this ?g as long as both inputs of a comparator remain above the maximum common- mode input voltages.
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-19 15.4 a/d conversion methods the control bits in the acr provide various options to charge or discharge current through the cap pin in order to perform single-slope a/d conversions using an external capacitor from the cap pin to v ss as shown in figure 15-7 . the various a/d conversion triggering options are given in table 15-3 . figure 15-7. single-slope a/d conversion method the top three bits of the acr control the charging and discharging current into or out of the cap pin. these three bits will have no affect on the cap pin if the isen enable bit is cleared. any clearing of the isen bit will immediately disable both the unknown voltage on (? input charge time to match unknown discharge time to reset capacitor voltage on capacitor connected to (+) input maximum charge time to v dd ?1.5 vdc v dd ?1.5 vdc charge time = c x v x i v dd +5v ramp cap v ss cap pb4/an3 pb5/an2 pb6/an1 pb7/an0 unknown signals mc68HC05SB7 v dd +5v ramp cap v ss cap pb4/an3 pb5/an2 pb6/an1 pb7/an0 unknown signals mc68HC05SB7 reference voltage tm tm using an external voltage reference using v dd as voltage reference
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-20 rev 2.1 charge current source and the discharge device. since all these bits and the isen bit are cleared when the device is reset, the mc68HC05SB7 starts with the charge and discharge function disabled. the length of time required to reach the maximum voltage to be measured will determine the resolution of the reading. the time to ramp the external capacitor voltage to match the maximum voltage is dependent on: desired resolution. clock rate for timing function. any prescaling of the clock to the timing function. charging current to external capacitor. value of the external capacitor. the values of each parameter are related by the general equation: each parameter can also be expressed by the following equations: where the signal names and parameters used are given in table 15-4 . note noise on the system ground or the external ramping capacitor can cause the comparator to trip prematurely. therefore in any given application it is best to use the fastest possible ramp rate (shortest possible time). note the value of any capacitor connected directly to the cap pin should be limited to less than 2 m f. larger capacitances will create signal noise. t chg cv max i chg ----------------------- = t chg pn f osc ------------- = v max i chg p n cf osc ----------------------------- - = n v max cf osc i chg p --------------------------------------- = c i chg n p v max f osc ----------------------------- - =
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-21 note suf?ient time should be allowed to discharge the external capacitor or subsequent charge times will be shortened with resultant errors in timing conversion. note if the unknown voltage applied to the comparator is greater than its common- mode range (v dd 1.5 volts) the external capacitor will try to charge to the same level. this will cause both comparator inputs to be above the common-mode range and the output will be indeterminate. all a/d conversion software methods should have a maximum time check to determine if this case is occurring. table 15-5 gives examples of voltage ranges, resolution, ramp times and capaci- tor sizes for various conversion methods. table 15-4. a/d conversion signals and de?itions name function conditions i chg charging current on external ramping capacitor i chg = 80 - 120 m a i dis discharge current on external ramping capacitor i dis > 1 ma v cap voltage on external ramping capacitor v ss < v cap < (v dd ?1.5) v x voltage of unknown on (? input of voltage comparator v ss < v x < (v dd ?.5) v max maximum voltage on external ramping capacitor v max = v dd ?1.0 t chg time to charge external capacitor d t from v ss to v x t dis time to discharge external capacitor d t from v max to v ss c capacitance of external ramping capacitor 0.001 to 1.000 m f n number of counts for i chg to charge c to v x 0 to 65536 p prescaler into timing function f osc ? loop time for software timing f osc ? 8 for core timer f osc ? 8 for programmable timer f osc clock source frequency (excluding any prescaling) 0 to 4.2 mhz
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-22 rev 2.1 the general architecture of the mc68HC05SB7 and mode selection bits in the acr allow four methods based on simple single-slope a/d conversion. each of these methods is shown in the following ?ures: manual start and stop (mode 0) figure 15-8 . manual start and automatic discharge (mode 1) figure 15-9 . automatic start and stop from tof to icf (mode 2) figure 15-10 . automatic start and stop from ocf to icf (mode 3) figure 15-11 . the description of the signals and parameters used in these ?ures are given in table 15-4 . table 15-5. sample conversion timing bits counts v max (vdc) a/d method clock source f osc (mhz) t chg ( m s) c ( m f) 8 256 3.5 software loop (10 cycles) mode 0 (manual) ext pin oscillator 2.0 2560 0.073 8 256 3.5 programmable timer, mode 1 (tof to icf) vco 0.5 4096 0.117 ext pin oscillator 1.0 2048 0.059 2.0 1024 0.029 4.0 512 0.015 10 1024 3.5 programmable timer, mode 1 (tof to icf) vco 0.5 16384 0.468 ext pin oscillator 1.0 8192 0.234 2.0 4096 0.117 4.0 2048 0.059 12 4096 3.5 programmable timer, mode 1 (tof to icf) vco 0.5 65536 1.872 ext pin oscillator 1.0 32768 0.936 2.0 16384 0.468 4.0 8192 0.234
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-23 figure 15-8. a/d conversion - full manual control (mode 0) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 0 by clearing the chg, atd2 and atd1 control bits in the acr. software write. software. 1v cap falls to v ss . wait out minimum t dis time. v max , i dis , c x. 2 stop discharge and begin charge by setting chg control bit in acr. software write. software. 3 v cap rises to v x and comparator output trips, setting cpf. wait out t chg time. v x , i chg , c x. 4v cap reaches v max. wait out t chg time. v max , i chg , c x. 5 begin next discharge by clearing the chg control bit in the acr. software write. software. t dis (min) t chg x i chg c x t chg t dis v x = t max v max chg comp 0 tof ocf icf (min) v cap t dis v x 1 2 3 4 1 5
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-24 rev 2.1 figure 15-9. a/d conversion - manual/auto discharge control (mode 1) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 1 by clearing chg and atd2; and setting atd1 in the acr. software write. software. 1v cap falls to v ss . wait out minimum t dis time. v max , i dis , c x. 2 stop discharge and begin charge by setting chg control bit in acr. software write. software. 3 v cap rises to v x and comparator output trips, setting cpf which clears chg control bit in the acr. wait out t chg time. cpf clears chg control bit. v x , i chg , c x. t dis (min) t chg x i chg c x t chg t dis v x = v max chg comp 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 2
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-25 figure 15-10. a/d conversion - tof/icf control (mode 2) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 2 by clearing chg and atd1 and setting atd2 in the acr. software write. (icen bit also set) software. 1v cap falls to v ss . wait out minimum t dis time. v max , i dis , c x. 2 stop discharge and begin charge when the next tof sets the chg control bit in acr. timer tof sets the chg control bit in the acr. free-running timer counter overflow, f osc , p. 3 v cap rises to v x and comparator output trips, setting cpf which causes an icf from the timer and clears the chg control bit in acr. wait out t chg time. timer icf clears the chg control bit in the acr. v x , i chg , c x. t dis (min) t chg x i chg c x t chg t dis v x = v max chg comp 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 2 (tcap)
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-26 rev 2.1 figure 15-11. a/d conversion - ocf/icf control (mode 3) point action software/hardware action dependent variable(s) 0 begin initial discharge and select mode 3 by clearing chg and set- ting atd2 and atd1 in the acr. software write. (icen bit also set) software. 1 v cap falls to v ss . set timer output compare registers (ocru, ocrl) to desired charge start time. wait out minimum t dis time. software write to ocrh, ocrl. v max , i dis , c x , software. 2 stop discharge and begin charge when the next ocf sets the chg control bit in acr. timer ocf sets the chg control bit in the acr. free-running timer counter overflow, f osc , p. 3 v cap rises to v x and comparator output trips, setting cpf which causes an icf from the timer and clears the chg control bit in acr. wait out t chg time. timer icf clears the chg control bit in the acr. v x , i chg , c x. t dis (min) t chg x i chg c x t chg t dis v x = v max chg comp 0 tof ocf icf (min) v cap t dis v x 1 2 3 1 3 (tcap)
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-27 15.5 voltage measurement methods the various methods for obtaining a voltage measurement can use software tech- niques to express these voltages as absolute or ratiometric readings. note all a/d conversion methods should include a test for a maximum elapsed time in order to detect error cases where the inputs may be outside of the design speci?ation. 15.5.1 absolute voltage readings the absolute value of a voltage measurement can be calculated in software by ?st taking a reference reading from a ?ed source and then comparing subse- quent unknown voltages to that reading as a percentage of the reference voltage multiplied times the known reference value. the accuracy of absolute readings will depend on the error sources taken into account using the features of the analog subsystem and appropriate software as described in table 15-6 . as can be seen from this table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted compar- ator inputs, and averaging of multiple samples. table 15-6. absolute voltage reading errors error source accuracy improvements possible in hardware in software change in reference voltage provide closer tolerance reference calibration and storage of reference source over temperature and supply voltage change in magnitude of ramp current source not adjustable compare unknown with recent measurement from reference non-linearity of ramp current source vs. voltage not adjustable calibration and storage of voltages at 1/4, 1/2, 3/4 and fs change in magnitude of ramp capacitor provide closer tolerance ramp capacitor compare unknown with recent measurement from reference frequency shift in internal low-power oscillator use external oscillator with crystal compare unknown with recent measurement from reference frequency shift in external oscillator provide closer tolerance crystal compare unknown with recent measurement from reference sampling capacitor leakage use faster conversion times compare unknown with recent measurement from reference internal voltage divider ratio not adjustable compare unknown with recent measurement from reference or avoid use of divided input noise internal to mcu close decoupling at v dd and v ss pins and reduce supply source impedance average multiple readings on both the reference and the unknown voltage
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-28 rev 2.1 internal absolute reference if a stable source of v dd is provided, the reference measurement point can be internally selected. in this case the reference reading can be taken by setting the vref bit and clearing the mux7:0 bits in the amux register. this connects the channel selection bus to the v dd pin. alternatively, the internal bandgap voltage can be used as the reference measurement point, by setting the ibref bit in amux2 register and tsen bit in the miscellaneous control register. external absolute reference if a stable external source is provided, the reference measurement point can be any one of the channel selected pins from pb4 through pb7. in this case the refer- ence reading can be taken by setting the mux bit in the amux which connects channel selection bus to the pin connected to the external reference source. 15.5.2 ratiometric voltage readings the ratiometric value of a voltage measurement can be calculated in software by ?st taking a reference reading from a reference source and then comparing sub- sequent unknown voltages to that reading as a percentage of the reference value. the accuracy of ratiometric readings will depend on variety of sources, but will generally be better than for absolute readings. many of these error sources can be taken into account using the features of the analog subsystem and appropriate software as described in table 15-7 . as with absolute measurements most of the errors can be reduced by frequent comparisons to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples. internal ratiometric reference if readings are to be ratiometric to v dd , the reference measurement point can be internally selected. in this case the reference reading can be taken by setting the vref bit and clearing the mux7:0 bits in the amux register which connects the channel selection bus to the v dd pin. alternatively, the internal bandgap voltage can be used as the reference measurement point, by setting the ibref bit in amux2 register and tsen bit in the miscellaneous control register. noise external to mcu close decoupling of power supply, low source impedances, good board layout, use of multi-layer board average multiple readings on both the reference and the unknown voltage table 15-6. absolute voltage reading errors error source accuracy improvements possible in hardware in software
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-29 external ratiometric reference if readings are to be ratiometric to some external source, the reference measure- ment point can be connected to any one of the channel selected pins from pb4 through pb7. in this case the reference reading can be taken by setting the mux bit in the amux which connects channel selection bus to the pin connected to the external reference source. 15.6 voltage comparator features the internal comparator can also be used as simple voltage comparator. voltage comparator voltage comparator can be used as a simple comparator if its charge current source and discharge device are disabled by clearing the isen bit in the acr. if isen bit is set the internal ramp discharge device connected to cap may become active and try to pulldown any voltage source that may be connected to that pin. also, since voltage comparator is always connected to two of the port b i/o pins, these pins should be con?ured as inputs and have their software programmable pulldowns disabled. the required setup to use voltage comparator as a simple comparator are shown in table 15-8 . table 15-7. ratiometric voltage reading errors error source accuracy improvements possible in hardware in software change in reference voltage not required for ratiometric compare unknown with recent measurement from reference change in magnitude of ramp current source not required for ratiometric compare unknown with recent measurement from reference non-linearity of ramp current source vs. voltage not adjustable calibration and storage of voltages at 1/4, 1/2, 3/4 and fs change in magnitude of ramp capacitor not required for ratiometric compare unknown with recent measurement from reference frequency shift in internal low-power oscillator not required for ratiometric compare unknown with recent measurement from reference frequency shift in external oscillator not required for ratiometric compare unknown with recent measurement from reference sampling capacitor leakage use faster conversion times compare unknown with recent measurement from reference internal voltage divider ratio not required for ratiometric compare unknown with recent measurement from reference noise internal to mcu close decoupling at v dd and v ss pins and reduce supply source impedance average multiple readings on both the reference and the unknown voltage noise external to mcu close decoupling of power supply, low source impedances, good board layout, use of multi-layer board average multiple readings on both the reference and the unknown voltage
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-30 rev 2.1 15.7 current source features the internal current source connected to the cap pin supplies about 100 m a of current when the ramp discharge device is disabled and the current source is active. therefore this current source can be used in an application if the isen enable bit is set to power up the current source is enabled by setting the a/d con- version method to manual mode 0 (atd1 and atd2 cleared) and the charge cur- rent enabled (chg set). 15.8 sample and hold when using the internal sample capacitor to capture a voltage for later conver- sion, the hold and dhold bit must be cleared ?st before changing any channel selection. if both the hold (or dhold) bit and the channel selection are changed on the same write cycle, the sample may be corrupted during the switch- ing transitions. note the sample capacitor can be affected by excessive noise created with respect to the devices v ss pin such that it may appear to leak down or charge up depending on the voltage level stored on the sample capacitor. it is recommended to avoid switching large currents through the port pins while a voltage is to remain stored on the same capacitor. the additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown voltages near vss to be sampled and then shifted up past the comparator offset and the device offset caused by a single v ss return pin. the offset also provides a means to measure the internal v ss level regardless of the comparator offset in order to determine n off as described in section 15.5 . 15.9 port b interaction with analog inputs the analog subsystem is connected directly to the port b i/o pins without any intervening gates. it is therefore possible to measure the voltages on port b pins set as inputs; or to have the analog voltage measurements corrupted by port b pins set as outputs. table 15-8. voltage comparator setup conditions current source enable discharge device disable port b pin as inputs prog. timer input capture source isen = 0 isen = 0 ddrb4 = 0 ddrb5 = 0 icen = 0
august 27, 1998 general release specification mc68HC05SB7 analog subsystem motorola rev 2.1 15-31 15.9.1 port b pins as inputs all the port b pins will power up as inputs or return to inputs following a reset of the device since the bits in the port b data direction register will be reset. if any port b pins are to be used for analog voltage measurements they should be left as inputs. in this case, not only can the voltage on the pin be measured, but the ?ogic state of the port b pins to be read from location $0002. 15.10 noise sensitivity in addition to the normal effects of electrical noise on the analog input signal there can also be other noise related effects caused by the digital-to-analog interface. since there is only one v ss return for both the digital and the analog subsystems on the device, currents in the digital section may affect the analog ground refer- ence within the device. this can add voltage offsets to measured inputs or cause channel-to-channel crosstalk. in order to reduce the impact of these effects, there should be no switching of heavy i/o currents to or from the device while there is a critical analog conversion or voltage comparison in process. limiting switched i/o currents to 2 to 4 ma dur- ing these times is recommended. a noise reduction bene? can be gained with 0.1 m f bypass capacitors from each analog input (pb7:4) to the v ss pin. also, try to keep all the digital power supply or load currents from passing through any conductors which are the return paths for an analog signal.
general release specification august 27, 1998 motorola analog subsystem mc68HC05SB7 15-32 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 personality eprom motorola rev 2.1 16-1 section 16 personality eprom this section describes how to program the 64-bit personality eprom (peprom). figure 16-1 shows the structure of the bit programmable peprom subsystem. figure 16-1. personality eprom peprom status/control register single sense amplifier pedata 0 0 0 0 0 pepgm peprzf 8-to-1 column decoder and multiplexer 8-to-1 row decoder and multiplexer col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 v pp switch v pp switch peprom select register 0 0 peb5 peb4 peb3 peb2 peb1 peb0 row zero decoder internal data bus internal data bus irq /v pp reset reset
general release specification august 27, 1998 motorola personality eprom mc68HC05SB7 16-2 rev 2.1 16.1 peprom registers two i/o registers control programming and reading of the peprom: the peprom bit select register (pebsr). the peprom status and control register (pescr). 16.1.1 peprom bit select register (pebsr) the peprom bit select register (pebsr) selects one of 64 bits in the peprom array. reset clears all the bits in the peprom bit select register. peb7 and peb6 ?not connected to the peprom array these read/write bits are available as storage locations. reset clears peb7 and peb6. peb5?eb0 ?peprom bit select bits these read/write bits select one of 64 bits in the peprom as shown in table 16-1 . bits peb2? select the peprom row, and bits peb5? select the peprom column. reset clears peb5?eb0, selecting the peprom bit in row zero, column zero. 16.1.2 peprom status and control register (pescr) the peprom status and control register (pescr) controls the peprom pro- gramming voltage. this register also transfers the peprom bits to the internal data bus and contains a ?g bit when row zero is selected. pedata ?peprom data this read-only bit is the state of the peprom sense ampli?r and shows the state of the currently selected bit. reset does not affect the pedata bit. 1 = peprom data is a logic one. 0 = peprom data is a logic zero. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pebsr r peb7 peb6 peb5 peb4 peb3 peb2 peb1 peb0 $000e w reset: 00000000 figure 16-2. peprom bit select register (pebsr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pescr r pedata 0 pepgm 0000 peprzf $000f w reset: u 0000001 u = unaffected by reset figure 16-3. peprom status and control register (pescr)
august 27, 1998 general release specification mc68HC05SB7 personality eprom motorola rev 2.1 16-3 pepgm ?peprom program control this read/write bit controls the switches that apply the programming voltage on the irq /v pp pin to the selected peprom cell. reset clears the pepgm bit. 1 = programming voltage applied to array bit. 0 = programming voltage not applied to array bit. peprzf ?peprom row zero flag this read-only bit is set when the peprom bit select register selects the ?st row (row zero) of the peprom array. selecting any other row clears peprzf. monitoring peprzf can reduce the code needed to access one byte of eight peprom locations. reset clears the peprom bit select register thereby set- ting the peprzf bit by default. 1 = row zero selected. 0 = row zero not selected. 16.2 peprom programming the peprom can be programmed by user software with the v pp voltage level applied to the irq /v pp pin. the following sequence shows how to program each peprom bit: 1. select a peprom bit by writing to the pebsr. 2. set the pepgm bit in the pescr. 3. wait 3 milliseconds. 4. clear the pepgm bit. 5. move to next peprom bit to be programmed in step 1. table 16-1. peprom bit selection pebsr peprom bit selected $00 - $07 row 0 - row 7 column 0 $08 - $0f row 0 - row 7 column 1 $10 - $17 row 0 - row 7 column 2 $18 - $1f row 0 - row 7 column 3 $20 - $27 row 0 - row 7 column 4 $28 - $2f row 0 - row 7 column 5 $30 - $37 row 0 - row 7 column 6 $38 - $3f row 0 - row 7 column 7
general release specification august 27, 1998 motorola personality eprom mc68HC05SB7 16-4 rev 2.1 note while the pepgm bit is set and the v pp voltage level is applied to the irq /v pp pin, do not access bits that are to be left unprogrammed (erased). to program the peprom, v dd must be greater than 4.5 vdc. 16.3 peprom reading the following sequence shows how to read the peprom: 1. select a bit by writing to the pebsr. 2. read the pedata bit in the pescr. 3. store the pedata bit in ram or in a register. 4. select another bit by changing the pebsr. 5. continue reading and storing the pedata bits until the required personality eprom data is retrieved and stored. reading the peprom is easiest when each peprom column contains one byte. selecting a row 0 bit selects the ?st bit, and incrementing the peprom bit select register (pebsr) selects the next bit in row 1 from the same column. increment- ing pebsr seven more times selects the remaining bits of the column and ends up selecting the bit in row 0 of the next column, thereby setting the row 0 ?g, peprzf. note a peprom byte that has been read can be transferred to the personality eprom bit select register (pebsr) so that subsequent reads of the pebsr quickly yield that peprom byte. 16.4 peprom erasing mcus with windowed packages permit peprom erasure with ultraviolet light. erase the peprom by exposing it to 15 ws/cm 2 of ultraviolet light with a wave- length of 2537 angstroms. position the ultraviolet light source 1 inch from the win- dow. do not use a shortwave ?ter. the erased state of a peprom bit is a logic zero.
august 27, 1998 general release specification mc68HC05SB7 personality eprom motorola rev 2.1 16-5 16.5 peprom preprogrammed options the mc68HC05SB7 is available with a factory preprogrammed peprom. the fol- lowing measured parameters are available: the internal vco minimum frequency: [programmed or left blank] the internal vco maximum frequency: [programmed or left blank] the internal bandgap reference voltage: [programmed or left blank] the internal temperature sensor voltage: [programmed or left blank] each parameter is stored as a 16-bit value in the peprom, as shown in the table 16-1 . unprogrammed bits are blank, and are available for user programming. 16.5.1 data format in preprogrammed peprom the 16-bit value is a binary representation of the measured data (4 digits, with the decimal point removed). some examples are shown below. for a measured data for f vcomin =1.500mhz, it is converted to 1500 or 5dc (hex) and the hex data is programmed as 0000 0101 1101 1100. for a measured data for f vcomax =5.800mhz, it is converted to 5800 or 16a8 (hex) and the hex data is programmed as 0001 0110 1010 1000. for a measured data for v ib =1.211v, it is converted to 1211 or 4bb (hex) and the hex data is programmed as 0000 0100 1011 1011. for a measured data for v temp =836.0mv, it is converted to 8360 or 20a8 (hex) and the hex data is programmed as 0010 0000 1010 1000. table 16-2. peprom preprogrammed option pebsr (lsb - msb) data $00 - $0f vco minimum frequency (f vcomin ) $10 - $1f vco maximum frequency (f vcomax ) $20 - $2f internal bandgap voltage (v ib ) $30 - $3f temperature sensor voltage 1 note: 1. measured at 80 c
general release specification august 27, 1998 motorola personality eprom mc68HC05SB7 16-6 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-1 section 17 instruction set this section describes the addressing modes and instruction types. 17.1 addressing modes the cpu uses eight addressing modes for ?xibility in accessing data. the addressing modes de?e the manner in which the cpu ?ds the data required to execute an instruction. the eight addressing modes are the following: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 17.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?g (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 17.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?st byte, and the immediate data value is the second byte.
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-2 rev 2.1 17.1.3 direct direct instructions can access any of the ?st 256 memory addresses with two bytes. the ?st byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 17.1.4 extended extended instructions use only three bytes to access any address in memory. the ?st byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 17.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?st 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 17.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?st 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?st 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-3 17.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?st byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 17.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?ds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?s that it is within the span of the branch. 17.1.9 instruction types the mcu instructions fall into the following ?e categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-4 rev 2.1 17.1.10 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu ?ds the other operand in memory. table 17-1 lists the register/memory instructions. table 17-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-5 17.1.11 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?d value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 17-2 lists the read-modify-write instructions. 17.1.12 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the ?st 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?ds the conditional branch destination by adding the table 17-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one? complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two? complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-6 rev 2.1 third byte to the program counter if the speci?d bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 17-3 lists the jump and branch instructions. table 17-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-7 17.1.13 bit manipulation instructions the cpu can set or clear any writable bit in the ?st 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?st 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?st 256 memory locations. bit manipulation instructions use direct addressing. table 17-4 lists these instructions. 17.1.14 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 17-5 , use inherent addressing. table 17-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 17-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-8 rev 2.1 17.1.15 instruction set summary table 17-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 17-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-9 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 17-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-10 rev 2.1 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one? complement) m ? ( ) = $ff ?(m) a ? ( ) = $ff ?(m) x ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 17-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc m a x m m
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? conditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two? complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 17-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0
general release specification august 27, 1998 motorola instruction set mc68HC05SB7 17-12 rev 2.1 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 17-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 b0 b7 c
august 27, 1998 general release specification mc68HC05SB7 instruction set motorola rev 2.1 17-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two? complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 17-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
motorola instruction set mc68HC05SB7 17-14 rev 2.1 table 17-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb m s b lsb msb
august 27, 1998 general release specification mc68HC05SB7 electrical specifications motorola rev 2.1 18-1 section 18 electrical specifications this section describes the electrical and timing speci?ations of the mc68HC05SB7. 18.1 maximum ratings note maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. the device is not intended to operate at these conditions. the mcu contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range from v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . 18.2 operating temperature range 18.3 thermal characteristics rating symbol value unit supply voltage v dd 0.3 to +7.0 v bootloader mode (irq /v pp pin only) v in v ss ?0.3 to 17 v current drain per pin excluding v dd and v ss i25ma operating junction temperature t j +150 c storage temperature range t stg 65 to +150 c characteristic symbol value unit operating temperature range mc68HC05SB7 (standard) t a t l to t h 0 to +70 c characteristic symbol value unit thermal resistance soic ssop q ja q ja 60 60 c/w c/w
general release specification august 27, 1998 motorola electrical specifications mc68HC05SB7 18-2 rev 2.1 18.4 supply current characteristics notes: 1. v dd as indicated, v ss = 0 v, t l t a t h , unless otherwise noted. 2. all values shown re?ct average measurements. 3. typical values at midpoint of voltage range, 25 c only. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 pin or inter- nal oscillator, all inputs 0.2 vdc from either supply rail (v dd or v ss ); no dc loads, less than 50pf on all outputs, c l = 20pf on osc2. 5. wait, stop i dd : all ports con?ured as inputs, v il = 0.2 vdc, v ih = v dd ?0.2 vdc. 6. stop i dd measured with osc1 = v dd . 7. wait i dd is affected linearly by the osc2 capacitance. 18.5 peprom programming characteristics notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. characteristic symbol min typ max unit v dd = 4.5 to 5.5 vdc run, all analog and lvr enabled internal vco at 2.5khz external oscillator at 4.2mhz wait internal vco at 2.5khz external oscillator at 4.2 mhz stop - all clocks disabled all analog/lvr disabled and csa enabled all analog and lvr disabled all analog disabled and lvr enabled all analog and lvr enabled i dd i dd i dd i dd i dd i dd i dd i dd 3 4.8 1 1.3 280 6 8 200 5 8 1.5 2 500 10 20 350 ma ma ma ma m a m a m a m a characteristic symbol min typ max unit peprom programming voltage v pp 13.7 v peprom programming current i pp 3 10 ma peprom programming time per byte t epgm 2ms
august 27, 1998 general release specification mc68HC05SB7 electrical specifications motorola rev 2.1 18-3 18.6 dc electrical characteristics notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. 2. all values shown re?ct average measurements. 3. typical values at midpoint of voltage range, 25 c only. characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = 10.0 m a v ol v oh v dd ?0.1 0.1 v v output high voltage (i load = 0.8 ma) pa0:7, pb1:7, pc4:7, reset v oh v dd ?0.8 v output low voltage (i load = 1.6 ma) pa0:7, pb1:7, pc4:7, reset v ol 0.4 v high source current (v oh = v dd ?0.5 to 1.0 vdc) source current per pin, pa0:7, pb1:7, pc4:7 source current total for all pins i oh i oh 4 ma ma high sink current (v ol = v ss + 1.5 vdc) sink current per pin, pa0:7, pb1:7, pc4:7 sink current total for all pins i ol i ol 12 ma ma high source current (v oh = v dd ?0.2vdc) source current for pin, esv i oh 3ma input high voltage pa0:7, pb1:7, pc4:7, reset , osc1, irq /v pp v ih 0.7 x v dd ? dd v input low voltage pa0:7, pb1:7, pc4:7, reset , osc1, irq /v pp v il v ss 0.3 x v dd v input current pa0:7, pb1:7, pc4:7, reset , osc1, irq /v pp i in 1 m a i/o ports high-z leakage current pa0:7, pb1:7, pc4:7 i oz 10 m a internal bandgap voltage v bg 1.1 1.2 1.3 v internal temperature sensor temperature gradient 2.0 2.2 2.4 mv/ c
general release specification august 27, 1998 motorola electrical specifications mc68HC05SB7 18-4 rev 2.1 18.7 analog subsystem characteristics notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. characteristic symbol min max unit voltage comparator input offset voltage v io 510mv voltage comparator input common-mode range v cmr ? dd ?1.5 v voltage comparator supply current i cmp 150 m a voltage comparator input divider ratio r div 0.49 0.51 external capacitor current source i source 80 120 m a current source supply current i ramp 220 m a source current linearity i ramp 1.0 %fs discharge sink current (v out = 0.4 v) i dis 0.8 ma external capacitor voltage range v in v ss v dd ?1.5 v comparator input impedance comparator used as comparator only (dhold =0) used as a/d function (dhold =1) z in z in 0.8 80 m w k w multiplexer switch resistance r mux 4.5 7 k w internal sample & hold capacitor capacitance charge/discharge time (0 to 3.5 vdc, dhold =0) charge/discharge time (0 to 3.5 vdc, dhold =1) c sh t shchg t shdchg 4 20 60 6 pf m s m s
august 27, 1998 general release specification mc68HC05SB7 electrical specifications motorola rev 2.1 18-5 18.8 control timing notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. 2. due to process variations, operating voltages, and temperature requirements, the quoted vco fre- quencies are typical limits, and should be treated as reference only. it is the users responsibility to ensure that the resulting internal operating frequency meets users requirement by setting the appropri- ate value in the vco adjust register. 3. the minimum period t ilil should not be less than the number of cycle times it takes to execute the inter- rupt service routine plus 21 t cyc . characteristic symbol min max unit frequency of oscillation (osc) crystal oscillator option external clock source internal vco (sclk = 0) 2 internal vco (sclk = 1) 2 f osc f osc f osc f osc 0.1 dc 1.5 0.5 4.2 4.2 5.8 4 mhz mhz mhz khz internal operating frequency, crystal or external clock (f osc /2) crystal oscillator option external clock source f op f op 0.05 dc 2.1 2.1 mhz mhz cycle time crystal oscillator or external clock source t cyc 476 ns timer resolution input capture (tcap) pulse width t resl t th , t tl 4.0 284 t cyc ns interrupt pulse width low (edge-triggered) t ilih 284 ns interrupt pulse period t ilil see note 3 t cyc osc1 pulse width (external clock input) t oh ,t ol 110 ns voltage comparator switching time (10 mv overdrive, either input) t prop ?0 m s voltage comparator power up delay (bias circuit already powered up) t delay 100 m s external capacitor switching time (i dis to i ramp )t prop ?0 m s external capacitor current source power up delay (bias circuit already powered up) t delay 100 m s bias circuit power up delay t delay 100 m s
general release specification august 27, 1998 motorola electrical specifications mc68HC05SB7 18-6 rev 2.1 18.9 reset characteristics notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. 2. by design, not tested. figure 18-1. stop recovery timing diagram characteristic symbol min typ max unit low voltage reset rising recovery voltage falling reset voltage lvr hysteresis v lvrr v lvrf v lvrh 1.3 1.2 100 2.3 2.2 3.1 3.0 v v mv por recovery voltage 2 v por 0 100 mv por v dd slew rate 2 rising falling s vddr s vddf 0.1 0.05 v/ m s v/ m s reset pulse width (when bus clock active) t rl 1.5 t cyc reset pulldown pulse width (from internal reset) t rpd 3?t cyc pch new 1ffe t rl osc1 1 reset internal clock 3 internal address bus 3 4096 t cyc 2 notes: 1. represents the internal gating of the osc1 pin. 2. normal delay of 4064 t cyc. 3. internal timing signal and data information not available externally. internal data bus 3 1fff new pch new pcl pcl new code op
august 27, 1998 general release specification mc68HC05SB7 electrical specifications motorola rev 2.1 18-7 figure 18-2. internal reset timing diagram figure 18-3. low voltage reset timing diagram pch new 1ffe t rpd reset internal clock 3 internal address bus 3 4096 t cyc 2 notes: 1. represents the internal reset from low voltage reset, illegal opcode fetch or cop watchdog timeout. 2. normal delay of 4064 t cyc. 3. internal timing signal and data information not available externally. internal data bus 3 1fff new pch new pcl pcl new internal reset 1 pin pch new 1ffe t rpd reset internal clock 3 internal address bus 3 4096 t cyc 2 notes: 1. reset pin pulled down be internal device. 2. normal delay of 4064 t cyc. 3. internal timing signal and data information not available externally. internal data bus 3 1fff new pch new pcl pcl new v dd pin 1 low voltage reset v lvrh v lvrl
general release specification august 27, 1998 motorola electrical specifications mc68HC05SB7 18-8 rev 2.1 18.10 sm-bus dc electrical characteristics notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. 2. for sm-bus speci?ation: logic "low"=0.6v or less; logic "high"=1.4v or above. 18.11 sm-bus control timing 18.11.1sm-bus interface input signal timing notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. 18.11.2sm-bus interface output signal timing notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. characteristic symbol min max unit low level input voltage v il v ss 0.3 x v dd v high level input voltage v ih 0.7 x v dd 5.5 v low level output voltage (open drain); at 2.86ma sink current (r pullup =1.7k w and c load =400pf) v ol v ss 0.135 v parameter symbol min max unit start condition hold time t hd.sta 2t cyc clock low period t low 4.7 t cyc sda/scl rise time t r ? m s data hold time t hd.dat 300 ns sda/scl fall time t f 300 ns clock high period t high 4t cyc data set up time t su.dat 250 ns start condition set up time (for repeated start condition only) t su.sta 2t cyc stop condition set up time t su.sto 2t cyc parameter symbol min max unit start condition hold time t hd.sta 8t cyc clock low period t low 11 t cyc sda/scl rise time t r ? m s data hold time t hd.dat 300 ns sda/scl fall time t f 300 ns clock high period t high 11 t cyc data set up time t su.dat t low ? cyc ?s start condition set up time (for repeated start condition only) t su.sta 10 t cyc stop condition set up time t su.sto 10 t cyc
august 27, 1998 general release specification mc68HC05SB7 electrical specifications motorola rev 2.1 18-9 figure 18-4. sm-bus timing diagram sda scl t hd.sta t low t hd.dat t high t su.dat t su.sta t su.sto t r t f
general release specification august 27, 1998 motorola electrical specifications mc68HC05SB7 18-10 rev 2.1
august 27, 1998 general release specification mc68HC05SB7 mechanical specifications motorola rev 2.1 19-1 section 19 mechanical specifications this section provides the mechanical dimensions for the 28-pin soic and 28-pin ssop packages. 19.1 28-pin soic (case 751f)

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general release specification august 27, 1998 motorola mechanical specifications mc68HC05SB7 19-2 rev 2.1 19.2 28-pin ssop -d- a - t - e b a 1 n 1.00 dia. h 3 4 4 a 2 6 side view end view top view seating plane -e- 1 2 3 see detail "a" - c - 2.36 bottom view e/2 d/2 1.00 1.00 dia. pin 7 8 p i n e s - p h i l i p c 0.076 m +e m 0.20 s d 0.12 m t e + b1 c b c1 base metal 8 10 section g-g with lead finish 12-16 parting line detail 'a' 5 l1 g g 0.25 bsc gauge plane seating plane l 0 min. 0.235 min r 7. 6. controlling dimension: millimeters. 9. 1. maximum die thickness allowable is 0.43mm (.017 inches). allowable dambar protrusion shall be 0.13mm total in dimension b does not include dambar protrusion/intrusion. 8. one another within 0.08mm at seating plane. 5. 4. 3. 2. formed leads shall be planar with respect to terminal positions are shown for reference only. for soldering to a substrate. dimension is the length of terminal protrusions shall not exceed 0.15mm per side. at the parting line, mold flash or do include mold mismatch and are measured include mold flash or protrusions, but "d" & "e" are reference datums and do not "t" is a reference datum. notes: dimensioning & tolerances per ansi.y14.5m-1982. excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07mm at least material condition. 10. these dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. this package outline drawing complies with jedec specification no. mo-150 for the lead counts shown 11. 8 0 dimensions in mm min. max. l 1 n h e e d a a o l y m b s nom. 4 a 2 0.65 bsc 1.86 0.13 1.73 1.78 0.21 1.99 1.73 0.05 1.68 5.20 5.30 5.38 7.65 0.63 0.75 7.80 7.90 0.95 28 10.07 10.20 10.33 b 0.25 0.38 b1 0.25 0.30 0.33 c1 0.09 0.15 0.16 c 0.09 0.20 1.25 ref. l1 o n e t 6 4 4 5 10 8,10 10 10 r 0.09 0.15 .407 .402 .397 28 .037 .311 .307 .030 .025 .301 .212 .209 .205 .066 .002 .068 .078 .008 .070 .068 .005 .073 .0256 bsc 4 nom. max. min. dimensions in inch 08 .010 .015 .010 .012 .013 .004 .008 .004 .006 .006 .049 ref. .004 .006 m m
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 a-1 appendix a mc68hc705sb7 this appendix describes the mc68hc705sb7, the emulation part for mc68HC05SB7. the entire mc68HC05SB7 data sheet applies to the mc68hc705sb7, with exceptions outlined in this appendix. a.1 introduction the mc68hc705sb7 is an eprom version of the mc68HC05SB7, and is avail- able for user system evaluation and debugging. the mc68hc705sb7 is function- ally identical to the mc68HC05SB7 with the exception of the 6106 bytes user rom is replaced by 6106 bytes user eprom. the mask option for the external pin oscillator on the mc68HC05SB7 is controlled by the mask option register at $002f on the mc68hc705sb7. this device is available in 28-pin soic package. a.2 memory the mc68hc705sb7 memory map is shown on figure a-1 . $0000 i/o registers 48 bytes $002f $0030 unimplemented 16 bytes $003f $0040 user ram 224 bytes stack ram 64 bytes $00c0 $011f $00ff $0120 unimplemented 1248 bytes $05ff $0600 user eprom 6144 bytes $1dff $1e00 bootloader rom 496 bytes $1fef $1ff0 user vectors 16 bytes $1fff figure a-1. mc68hc705sb7 memory map
general release specification august 27, 1998 motorola mc68HC05SB7 a-2 rev 2.1 a.3 personality eprom (peprom) the 64-bit peprom is left blank for user programming. a.4 mask option register the eprom programmable mask option register is used for setting eprom security and enabling the external pin oscillator. epmsec ?eprom security bit 1 = access to the eprom array in non-user mode is denied. 0 = access to the eprom array in non-user mode is enabled. this write-only bit controls the non-user mode access to the eprom array on the mcu. when programmed to ?? any accesses of the eprom locations will return unde?ed results. epmsec programming the state of the epmsec security bit should be programmed using a programmer board (available from motorola). in order to program the epmsec bit the desired state must be written to the mor address and then the mpgm bit in the eprog register must be used. the following sequence will program the epmsec bit: 1. write the desired data to the epmsec bit in mor. 2. apply the programming voltage to the irq /v pp pin. 3. set the mpgm bit in the eprog. 4. wait for the programming time (t mpgm ). 5. clear the mpgm bit in the eprog. 6. remove the programming voltage from the irq /v pp pin. once the epmsec bit has been programmed to a ?? access to the contents of the eprom in the non-user mode will be denied. it is therefore recommended that the user eprom in the part ?st be programmed and fully veri?d before setting the epmsec bit. oscs ?oscillator select bit 1 = external pin oscillator (epo) enabled. 0 = external pin oscillator (epo) disabled. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mor r epmsec oscs ------ $002f w reset: uuuuuuuu erased: 0 0 ------ u = unaffected by reset figure a-2. mc68hc705sb7 mask option register (mor)
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 a-3 the oscs bit enables the osc1 and osc2 pins for external oscillator connec- tion. osc1 replaces pb2/cs0 and osc2 replaces pb3/cs1. this is selected by a mask option on the mc68HC05SB7 device. a.5 bootloader mode bootloader mode is entered upon the rising edge of reset if irq /v pp pin is at v tst and pb1/tcap at v dd . the bootloader program is masked in the rom area from $1e00 to $1fef. this program handles copying of user code from an exter- nal eprom into the on-chip eprom. the bootload function has to be done from an external eprom. the bootloader performs one programming pass at 1ms per byte then does a verify pass. a.6 eprom programming this section describes how to program the 6160-byte eprom and the eprom security bit. in packages with no quartz window, the eprom functions as one-time program- mable rom (otprom) programming the on-chip eprom is achieved by using the program control reg- ister located at address $001e. the programming software copies to the 6144-byte space located at eprom addresses $0600 ?$1dff and to the 16-byte space at addresses $1ff0 ?$1fff which includes the mask option register (mor) at address $002f. please contact motorola for programming board availability. a.6.1 eprom programming register (eprog) the eprom programming register shown in figure a-3 contains the control bits for programming the eprom and mor. in normal operation, the eprom pro- gramming register is a read-only register that contains all logic zeros. epgm ?eprom programming this read/write bit applies the voltage from the irq /v pp pin to the eprom. to write the epgm bit, the elat bit must already be set. clearing the elat bit also clears the epgm bit. reset clears epgm. 1 = eprom programming power switched on. 0 = eprom programming power switched off. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eprog r 00000 elat mpgm epgm $001c w reset: 00000000 unimplemented reserved for test figure a-3. eprom programming register (eprog)
general release specification august 27, 1998 motorola mc68HC05SB7 a-4 rev 2.1 mpgm ?mask option register (mor) programming this read/write bit applies programming power from the irq /v pp pin to the mor. reset clears mpgm. 1 = mor programming power switched on. 0 = mor programming power switched off. elat ?eprom bus latch this read/write bit con?ures address and data buses for programming the eprom array. eprom data cannot be read when elat is set. clearing the elat bit also clears the epgm bit. reset clears elat. 1 = address and data buses con?ured for eprom programming of the array. the address and data bus are latched in the eprom array when a subsequent write to the array is made. data in the eprom array cannot be read. 0 = address and data buses con?ured for normal operation. whenever the elat bit is cleared the epgm bit is also cleared. both the epgm and the elat bit cannot be set using the same write instruction. any attempt to set both the elat and epgm bit on the same write instruction cycle will result in the elat bit being set and the epgm bit being cleared. a.6.2 programming sequence the eprom programming sequence is: 1. set the elat bit in the eprog register. 2. write the desired data to the desired eprom address. 3. set the epgm bit in the eprog register for the speci?d programming time (t epgm ). 4. clear the epgm bit 5. clear the elat bit the last two steps must be performed with separate cpu writes. caution it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. figure a-4 shows the ?w required to successfully program the eprom.
august 27, 1998 general release specification mc68HC05SB7 motorola rev 2.1 a-5 a.7 eprom erasing mcus with windowed packages permit eprom erasure with ultraviolet light. erase the eprom by exposing it to 15 ws/cm 2 of ultraviolet light with a wave- length of 2537 angstroms. position the ultraviolet light source 1 inch from the win- dow. do not use a shortwave ?ter. the erased state of an eprom bit is a logic one. start elat=1 write eprom byte epgm=1 wait 1ms epgm=0 elat=0 write additional byte? n y end figure a-4. eprom programming sequence
general release specification august 27, 1998 motorola mc68HC05SB7 a-6 rev 2.1 a.8 eprom programming specifications notes: 1. v dd =5v 10%, v ss = 0 v, t l t a t h , unless otherwise noted. characteristic symbol min typ max unit mor programming time t mpgm 4 m s eprom programming voltage v pp 13.7 v eprom programming current i pp ? 5ma eprom programming time per byte t epgm 4 m s

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